Vector processing system for invalidating scalar cache memory bl

Details Vector processing system for invalidating scalar cache memory bl Vector processing system for invalidating scalar cache memory bl

1990-03-27

1993-09-21

Lee, Thomas C.

Boots, shoes, and leggings

395375, 364736, 364DIG1, 3642281, 36423221, 3642434, G06F 15347

Patent

active

052476359

ABSTRACT:
A data processing apparatus includes an instruction issuing unit, an interval holding unit, a passing control unit, and a nullification processing unit. The instruction issuing unit tentatively issues a vector store instruction having no definitive data as an instruction not subjected to actual vector store processing. The interval holding unit obtains and holds a store interval block address to be operated by the vector store instruction tentatively issued from the instruction issuing unit. The passing control unit compares a block address indicated by a scalar load/store instruction issued from the instruction issuing unit with the store interval block address held by the interval holding unit. If the block address falls within the range of the store interval block addresses, the passing control unit causes processing for the scalar load/store instruction to wait until the vector store instruction is finally issued from the instruction issuing unit and processed. When a vector store instruction is tentatively issued from the instruction issuing unit, the nullification processing unit nullifies block data present in a store cache memory of a buffer storing unit of the apparatus and corresponding to a store address of the vector store instruction.

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Hwang et al, "Proceedings of the 1986 International Conference on Parallel Processing", IEEE Computer Society, Aug. 19-22, 1986, pp. 516-518.

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