Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2006-06-27
2006-06-27
Treat, William M. (Department: 2181)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
Reexamination Certificate
active
07069417
ABSTRACT:
A vector processing system for executing vector instructions, each instruction defining multiple value pairs, an operation to be executed and a modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and, when selected, to implement an operation on said value pair to generate a result, each processing unit comprising at least one flag and being selectable in dependence on a condition defined by said at least one flag, wherein the modifier defines the condition under which the parallel processing unit is individually selected.
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Bailey Neil
Barlow Stephen
Plowman David
Ramsdale Timothy
Swann Robert
Broadcom Corporation
McAndrews Held & Malloy
Treat William M.
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