Vector processing apparatus including timing generator to activa

Details Vector processing apparatus including timing generator to activa Vector processing apparatus including timing generator to activa

1990-04-05

1993-10-05

Kulik, Paul V.

Boots, shoes, and leggings

395550, 364DIG1, 36423221, 364251, 3642514, G06F 15347

Patent

active

052513238

ABSTRACT:
In vector processing apparatus comprising operand vector registers (11a, 12a) each storing a plurality of vector operand elements, each of readout units (16a, 17a) successively reads a predetermined number of the vector operand elements out of the respective operand vector registers at a predetermined cycle time. The vector operand elements are supplied to arithmetic logic units (25, 30) from the respective operand vector registers. One of the arithmetic logic units is supplied with result elements from another of the arithmetic logic units. The predetermined number of the result elements are successively written in a result vector register (32a) at the predetermined cycle time by a writing unit (33a). With this vector processing apparatus, it is possible to perform iterative operation in parallel at a high speed under simple control.

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Cheng, Hui, "Vector Pipelining, Chaining and Speed on the IBM 3090 and Cray X-MP," Computer, 1989, pp. 31-46.

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