Vector processing apparatus

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364730, G06F 738

Patent

active

047617535

ABSTRACT:
A vector operation processing apparatus utilizes a plurality of vector registers in a pipeline computer architecture. The vector registers store ordered data elements which are processed in a pipelined vector operation unit in response to a vector instruction which designates selected ones of the vector registers. An input selection circuit is utilized for writing results of the operation performed by the pipelined vector operation unit into the vector registers which are designated by the vector instruction. A write control device is used for causing the writing operation to be performed exclusively on the plurality of vector registers in response to an indication by the vector instruction.

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patent: 4685076 (1987-08-01), Yoshida
Kogge, Peter M., "The Architecture of Pipelined Computers", McGraw-Hill, 1981, pp. 1-6.

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