Electrical computers and digital processing systems: processing – Byte-word rearranging – bit-field insertion or extraction,...
Reexamination Certificate
1998-06-25
2001-01-23
Eng, David Y. (Department: 2783)
Electrical computers and digital processing systems: processing
Byte-word rearranging, bit-field insertion or extraction,...
Reexamination Certificate
active
06178500
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to consolidation of multimedia facilities and in particular to reusing existing circuitry for one multimedia instruction in place of comparable circuitry for other multimedia instructions. Still more particularly, the present invention relates to employing a crossbar within a vector permute unit for multiplexing functions required for other multimedia instructions.
2. Description of the Related Art
Multimedia applications are increasing, leading to an increased demand for multimedia facilities within processors. Processors, such as the PowerPC™ processor available from IBM Corporation of Armonk, N.Y., are increasingly incorporating such multimedia facilities. In the case of the PowerPC™, the multimedia facility is the vector multimedia extensions (VMX) facility.
Several of the instructions implemented by the VMX facility require a multiplexing function for at least one stage. For example, the traditional approach to implementing the vpack instruction, which compresses either 32 bits into 16 bits or 16 bits into 8 bits, would involve a multiplexer. An example is depicted in
FIG. 3. A
vpack instruction is received by decode logic
302
, which generates selects for multiplexer
304
based on whether the operand
306
is being compressed from 16 bits to 8 bits or from 32 bits to 16 bits. Multiplexer
304
selects possible alternatives for the top target byte
308
a
from the bytes of 32 bit operand
306
. Saturation multiplexers
310
a
and
310
b
, under the control of saturation detection logic
312
, select between source bytes from operand
306
or their saturated values
314
a
and
314
b
for target bytes
308
a
and
308
b
. Multiplexer
304
, in particular, requires a significant amount of area within the multimedia facility and may incur undesirable latency in instruction execution.
It would be desirable, therefore, to utilize existing hardware within the multimedia facilities of a processor to performing comparable multiplexing and shifting functions for other instructions. It would further be advantageous if the resulting mechanism reduced latencies for the instructions.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide a method and apparatus for consolidation of multimedia facilities.
It is another object of the present invention to provide a method and apparatus for reusing existing circuitry for one multimedia instruction in place of comparable circuitry for other multimedia instructions.
It is yet another object of the present invention to provide a method and apparatus for employing a crossbar within a vector permute unit for multiplexing functions required for other multimedia instructions.
The foregoing objects are achieved as is now described. A crossbar is implemented within multimedia facilities of a processor to perform vector permute operations, in which the bytes of a source operand are reordered in the target output. The crossbar is then reused for other instructions requiring multiplexing or shifting operations, particularly those in which the size of additional multiplexers or the size and delay of a barrel shifter is significant. A vector pack instruction with saturation detection, for example, may be performed with one cycle latency by the crossbar and a correction multiplexer for substituting saturated values. The crossbar facility thus gets reused with improved performance of the instructions now sharing the crossbar and a reduction in the total area required by a multimedia facility within a processor.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 5339396 (1994-08-01), Muramatsu et al.
patent: 5560028 (1996-09-01), Sachs
patent: 5794003 (1998-08-01), Sachs
patent: 5857111 (1999-01-01), Oda
patent: 5948096 (1999-09-01), Ginosar et al.
patent: 5978899 (1999-11-01), Ginosar et al.
Eng David Y.
England Anthony V. S.
Felsman Bradley Vaden Gunter & Dillon, LLP
International Business Machines - Corporation
LandOfFree
Vector packing and saturation detection in the vector... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Vector packing and saturation detection in the vector..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vector packing and saturation detection in the vector... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2502195