Vector floating point unit

Details Vector floating point unit Vector floating point unit

2005-07-26

2005-07-26

Pan, Daniel H. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Vector processor

C712S222000, C711S219000, C710S317000, C708S495000

Reexamination Certificate

active

06922771

ABSTRACT:
The present invention provides a vector floating point unit (FPU) comprising a product-terms bus, a summation bus, a plurality of FIFO (first in first out) registers, a crossbar operand multiplexor coupled, a floating point multiplier, and a floating point adder. The floating point multiplier and the floating point adder are disposed between the crossbar operand multiplexor and the product-terms and summation buses, and are in parallel to each other. The invention also provides the configuration register and the command register in order to provide flexible architecture and the capability to fine-tune the performance to a particular application. The invention performs the multiplication operation and the addition operation in a pipelined fashion. Once the pipeline is filled, the invention outputs one multiplication output and one addition output at each clock cycle. The invention reduces the latency of the pipelined operation and improves the overall system performance by separating the floating point multiplier from the floating point adder so that the multiplication operation can be executed separately and independently of the addition operation.

REFERENCES:
patent: 4639886 (1987-01-01), Hashimoto et al.
patent: 4849923 (1989-07-01), Samudrala et al.
patent: 4974198 (1990-11-01), Ishii
patent: 5197140 (1993-03-01), Balmer
patent: 5805875 (1998-09-01), Asanovic
patent: 5923862 (1999-07-01), Nguyen et al.

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