Vector data processing apparatus wherein a time slot for access

Details Vector data processing apparatus wherein a time slot for access Vector data processing apparatus wherein a time slot for access

1995-06-02

1996-07-23

Kim, Ken S.

395297, 395304, 395405, 395483, 395484, 395495, 395496, 395826, 395865, G06F 13372

Patent

active

055399029

ABSTRACT:
A vector data processing apparatus having a set of vector registers, one or more memory access pipelines, and one or more composite calculation pipelines, wherein the vector registers consist of a plurality of banks, and each bank is independently accessible. Each of the pipelines can cyclically access each of the banks of the vector registers when one or more of a predetermined number of time slots, through each of which time slots the access is carried out, are assigned to an instruction using the pipeline. Immediately when a memory access instruction is received, a vector unit control circuit, which controls operations of the vector data processing apparatus, assigns a time slot for a newly-detected memory access instruction using a memory access pipeline, if it is determined that the memory access pipeline is available based on the pipeline operation status flags, and that the time slot is available based on the detected status of the predetermined number of time slots. Further, when a composite calculation instruction is received, the vector unit control circuit assigns one or more time slots .for the newly-detected composite calculation instruction using a composite calculation pipeline, if it is determined that the composite calculation pipeline is available based on the pipeline operation status flags, and that time slots are available based on the detected status of the predetermined number of time slots.

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