Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word
Reexamination Certificate
2008-05-20
2008-05-20
Kindred, Alford (Department: 2181)
Electrical computers and digital processing systems: processing
Processing architecture
Long instruction word
C712S022000, C712S023000, C712S034000, C712S035000
Reexamination Certificate
active
07376812
ABSTRACT:
A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one aspect, the processor supports three possible instruction sizes while maintaining the simplicity of programming and allowing efficient physical implementation. Most of the application code can be encoded using two sets of narrow size instructions to achieve high code density. Adding a third (and larger, i.e. VLIW) instruction size allows the architecture to encode multiple operations per instruction for the performance critical section of the code. Further, each operation of the VLIW format instruction can optionally be a SIMD operation that operates upon vector data. A scheme for the optimal utilization (highest achievable performance for the given amount of hardware) of multiply-accumulate (MAC) hardware is also provided.
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Huffman William A.
Kennedy James Robert
Killian Earl A.
Petkov Darin S.
Sanghavi Himanshu A.
Kindred Alford
Moll Jesse
Pillsbury & Winthrop
Tensilica, Inc.
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