VDT stress mitigating device and method, VDT stress risk...

Television – Image signal processing circuitry specific to television – Noise or undesired signal reduction

Reexamination Certificate

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Details

C348S625000, C348S665000, C382S260000, C382S264000

Reexamination Certificate

active

10867477

ABSTRACT:
The aim of the present invention is to provide a VDT stress mitigating device and method capable of mitigating VDT stress caused by a regular spatial pattern and VDT stress caused by flicker generated by an interlaced format, a VDT stress risk quantifying device and method, and a recording medium. An A/D conversion section10imports interlaced format video signals P1from an external image signal output device and converts them in field units by A/D conversion into image data D1. A filter section20, while not distinguishing between the first field and the second field, and while maintaining the temporal order of these fields, performs a temporal filtering process on the image data of each field. A D/A conversion section30converts the image data D2that has undergone the temporal filtering process by the filter section20into image signals P2based on an interlaced format by D/A conversion. The image signals P2are then sequentially outputs according to the temporal order of the fields.

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