VDS clamp for limiting impact ionization in high density CMOS de

Details VDS clamp for limiting impact ionization in high density CMOS de VDS clamp for limiting impact ionization in high density CMOS de

1986-11-14

1988-04-05

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, 307451, 307497, 307568, 307579, 307585, 330253, H03K 1716

Patent

active

047361174

ABSTRACT:
A circuit for controlling drain-to-source voltage in an MOS transistor. A second MOS transistor is located in series with the first transistor. The gate voltage of the second transistor is such that the drain-to-source voltages of both transistors are substantially equal.

REFERENCES:
patent: 4069430 (1978-01-01), Masuda
patent: 4317055 (1982-02-01), Yoshida et al.
patent: 4484089 (1984-11-01), Viswanathan
patent: 4490629 (1984-12-01), Barlow et al.
patent: 4508978 (1985-04-01), Reddy
patent: 4508982 (1985-04-01), Kapral et al.
patent: 4633425 (1986-12-01), Senderowicz

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