VDMOS/logic integrated circuit comprising a diode

Details VDMOS/logic integrated circuit comprising a diode VDMOS/logic integrated circuit comprising a diode

1990-07-26

1991-12-31

Mintel, William

357 42, 357 43, 357 52, 357023400, 357 41, H01L 2948, H01L 2956, H01L 2702, H01L 2934

Patent

active

050775863

ABSTRACT:
An integrated circuit includes a vertical power transistor, a depletion-mode lateral MOS logic transistor and a lateral Schottky diode in an N.sup.+ epitaxial semiconductor layer of an N substrate. The depletion-mode lateral transistor and Schottky diode are in a P well formed in the epitaxial layer during a first doping step. The vertical power transistor and depletion-mode lateral transistor include P.sup.+ semiconductor regions formed during a second doping step. The lateral transistor and Schottky diode include an N doped semiconductor channel layer formed during a third doping step so they have similar characteristics. The vertical power transistor includes a P doped semiconductor channel layer formed during a fourth doping step. The lateral transistor, Schottky diode and channel of the vertical power transistor include N.sup.30 doped semiconductor regions formed during a fifth doping step. The semiconductor region formed during the fifth step associated with the Schottky diode forms a ring around the layer of the diode formed during the third step. Metal electrodes are formed on regions of the transistors and diode as formed during the fifth step and on the diode layer formed during the third step and on regions formed during the second step. The layer formed during the third step forms a junction about 0.7.mu. below the substrate and has a surface dopant concentration of about 10.sup.16 atoms/cm.sup.3.

REFERENCES:
patent: 4811065 (1989-03-01), Cogan
patent: 4874714 (1989-10-01), Eklund
patent: 4887142 (1989-12-01), Bertotti et al.
"Silicon Processing for the ULSI ERA", Wolf, Lattice Press, 1990, pp. 321-322, Fig. 5-12.

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