VDD detection path in power-up circuit

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – For fault location

Reexamination Certificate

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Details

C327S143000, C327S198000

Reexamination Certificate

active

06759852

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a power-up detection scheme in an integrated circuit. More specifically, the present invention relates to a circuit for detecting when the V
DD
(core) voltage reaches the correct level for operating an associated circuit.
BACKGROUND OF THE INVENTION
FIG. 1
is a circuit diagram of a conventional V
DD
power-up detection circuit
100
and an associated circuit
111
, which is powered by a V
DD
supply voltage. V
DD
power-up detection circuit
100
includes n-channel MOS transistors
101
-
103
, p-channel MOS transistor
104
and Schmidt trigger circuit
110
. N-channel transistor
101
is a conventional thin oxide transistor of the type typically used in circuit
111
. N-channel transistor
103
is a thick oxide transistor, which has a gate oxide that is thicker than that of n-channel transistor
101
. N-channel transistor
101
has a threshold voltage of about 370 milli-Volts (mV). Thick oxide transistor
103
has a threshold voltage of about 430 mV. N-channel transistor
102
is a low-threshold voltage transistor (as indicated by the triangle in the channel region of this transistor), which has a threshold voltage of about 240 mV. An additional implant mask is required to form low-threshold voltage transistor
102
.
N-channel transistors
101
and
102
are connected in series between the V
DD
voltage supply terminal and the ground voltage supply terminal. More specifically, n-channel transistor
101
is coupled between the V
DD
voltage supply terminal and node N
01
, and n-channel transistor
102
is coupled between node N
01
and the ground voltage supply terminal. The gates of n-channel transistors
101
and
102
are commonly connected to the V
DD
voltage supply terminal.
P-channel transistor
104
and n-channel transistor
103
are connected in series between the V
DD
voltage supply terminal and the ground supply terminal. More specifically, p-channel transistor
104
is coupled between the V
DD
voltage supply terminal and node N
02
, and n-channel transistor
103
is coupled between node N
02
and the ground voltage supply terminal. The gate of p-channel transistor
104
is coupled to the ground voltage supply terminal, and the gate of n-channel transistor
103
is coupled to node N
01
. Node N
02
is coupled to provide a voltage V
02
to Schmidt trigger circuit
110
.
During power-up, the voltage on the V
DD
voltage supply terminal increases from a value of 0 Volts to the nominal V
DD
supply voltage. N-channel transistors
101
-
103
and p-channel transistor
104
are initially turned off when the V
DD
supply voltage is equal to 0 Volts. When the V
DD
supply voltage starts to increase, p-channel transistor
104
, which has a gate coupled to ground, ideally turns on first with the desired behavior of subthreshold conduction. Thus, the output voltage V
02
on node N
02
initially tracks the increasing V
DD
supply voltage.
As the V
DD
supply voltage increases, the low-threshold voltage n-channel transistor
102
will turn on faster than n-channel transistor
101
. As a result, the low-threshold voltage n-channel transistor
102
initially pulls down the voltage on node N
01
, thereby ensuring that n-channel transistor
103
remains off, and the output voltage V
02
on node N
02
continues to track the V
DD
supply voltage. In order for this to occur, the subthreshold conduction of transistor
101
must be less than the threshold conduction of transistor
102
.
As the V
DD
supply voltage continues to increase, n-channel transistor
101
turns on stronger, thereby causing the voltage on node N
01
to be pulled up. Eventually, the voltage on node N
01
becomes high enough to turn on n-channel transistor
103
. At this time, the voltage V
02
on node N
02
begins to be pulled down toward ground. Schmidt trigger circuit
110
detects when this voltage V
02
drops below the V
DD
supply voltage by a predetermined percentage. Upon detecting this voltage drop, trigger circuit
110
asserts a logic high enable signal EN
111
, which is used to activate circuit
111
. It is intended that circuit
111
is only enabled after the V
DD
supply voltage has reached an acceptable level for operating this circuit
111
.
However, in order for circuit
100
to operate as described above, the following conditions must be met by transistors
101
-
104
. First, the subthreshold conductance of low threshold voltage transistor
102
must be greater than the subthreshold conductance of transistor
101
, in order to ensure that node N
01
is not pulled up to the V
DD
supply voltage when the V
DD
supply voltage is less than the threshold voltage of low threshold voltage transistor
102
(240 mV). Second, the subthreshold conductance of transistor
101
must be less than the on-conductance of low threshold voltage transistor
102
, thereby ensuring that node N
01
is pulled down when the V
DD
supply voltage is greater than the threshold voltage of transistor
102
(240 mV), but less than the threshold voltage of transistor
101
(370 mV). Third, as the V
DD
supply voltage increases, the on-conductance of transistor
101
must become greater than the on-conductance of low threshold transistor
102
, thereby ensuring that node N
01
is eventually pulled up toward the V
DD
supply voltage. Fourth, the on-conductance of p-channel transistor
104
must be greater than the subthreshold conductance of n-channel transistor
103
, thereby ensuring that the voltage V
02
tracks the V
DD
supply voltage while the voltage on node N
01
is less than the threshold voltage of n-channel transistor
103
(430 mV). Finally, as the V
DD
supply voltage increases, the on-conductance of n-channel transistor
103
must become greater than the on-conductance of p-channel transistor
104
, thereby ensuring that node N
02
is eventually pulled down toward the ground supply voltage.
If the above-listed relationships are not true, circuit
100
may operate improperly. For example, if the subthreshold conductance of transistor
101
is greater than the on-conductance of low-threshold voltage transistor
102
, then the voltage on node N
01
may be pulled up toward the V
DD
supply voltage, thereby causing the voltage on node N
02
to be pulled low relative to the V
DD
supply voltage. In this case, Schmidt trigger circuit
110
may erroneously activate the enable signal EN
111
, before the V
DD
supply voltage has reached an acceptably high voltage. The same result may occur if the subthreshold conductance of transistor
101
is greater than the subthreshold conductance of transistor
102
, or if the subthreshold conductance of transistor
103
is greater than the on-conductance of p-channel transistor
104
.
Conversely, if the on-conductance of transistor
102
is greater than the on-conductance of transistor
101
, then the voltage on node N
01
may be pulled down toward the ground supply terminal, such that transistor
103
fails to turn on. In this case, the voltage V
02
will continue to be pulled up to the V
DD
supply voltage, and Schmidt trigger circuit
101
will not activate the enable signal EN
111
, even after the V
DD
supply voltage has reached an acceptable operating level. The same result may occur if the on-conductance of transistor
104
is greater than the on-conductance of transistor
103
.
As V
DD
supply voltages become smaller, approaching levels of 1.2 Volts and lower, the sub-threshold currents become larger, such that the above listed requirements cannot be reliably met. Moreover as the V
DD
supply voltage decreases, it becomes difficult to significantly increase the on-conductance of transistor
101
relative to the on-conductance of transistor
102
(i.e., the width of transistor
101
must become unrealistically large). In reality, it is difficult, if not impossible, to design transistors
101
and
102
such that transistor
101
is able to reliably overpower transistor
102
before the V
DD
supply voltage exceeds 700 mV.
It would therefore be desirable to have a circuit that is capable of reliably detecting when a V
DD
sup

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