VCXO with reduced PWM effects high slew rate conditions

Details VCXO with reduced PWM effects high slew rate conditions VCXO with reduced PWM effects high slew rate conditions

1999-07-14

2001-01-30

Pascal, Robert (Department: 2817)

Oscillators

Electromechanical resonator

Crystal

C331S1160FE

Reexamination Certificate

active

06181217

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to oscillators and particularly to voltage controlled crystal oscillators (hereafter “VCXO's”).
BACKGROUND OF THE INVENTION
The uses of VCXO's are well known. They are particularly useful, for example, in phase lock loop (PLL) applications for supplying a variable frequency output signal to the loop phase detector under the control of the loop filter for locking the output of the VCXO to the frequency (or a multiple thereof) of an input signal applied to the phase detector. Other uses are also quite well known.
FIG. 1
is an example of a conventional (prior art) VCXO of the Pierce type and comprises an inverting logic gate U
1
provided with a DC feedback path (feedback resistor Rf) for biasing the inverter U
1
to a linear operating region and an AC feedback path for causing oscillations to occur and for controlling the frequency of the oscillations in response to a frequency control signal, Vbias, applied to a control input terminal T
2
.
The AC feedback path
20
includes a source resistor Rx that is AC coupled via a capacitor C
1
to a first plate of a crystal X
1
and is coupled to ground via a first varactor tuning diode D
1
. The second plate
24
of crystal X
1
is coupled by a second varactor diode D
2
to ground and to the input
1
of the inverter U
1
via a DC blocking capacitor Cb. A bias voltage, Vbias, provided at an input terminal T
2
via a suitable source (not shown), is coupled via resistors R
1
and R
2
to varactor diodes D
1
and D
2
, respectively, for tuning the VCXO. The output
2
of inverter U
1
is coupled to an output terminal T
1
for supplying a clock output signal CL to external utilization circuitry (not shown). For purposes of illustration and explanation, exemplary element values are shown in the prior art example of FIG.
1
.
In operation, the feedback resistor Rf provides DC bias for biasing inverter U
1
to a linear operating region as previously noted. In the AC feedback path
20
, the crystal X
1
and the two varactor diodes D
1
and D
2
form a so-called “tank” circuit that determines and controls the oscillator frequency. As the control voltage (Vbias) at input terminal T
2
increases, the capacitance of the varactor diodes D
1
and D
2
decreases thereby increasing the frequency of the VCXO output clock signal CL at teminal T
1
. Conversely, a decrease in Vbias will decrease the frequency of the output clock signal, CL.
SUMMARY OF THE INVENTION
It is herein recognized that certain problems may arise when a conventional varactor tuned VCXO's (as in the example of
FIG. 1
) are used in an applications (e.g., in a PLL or other application) wherein the VCXO control voltage (Vbias) exhibits a relatively high rate of change or “slew” rate. Such a condition may be frequently encountered in PLL applications during loop acquisition. In television apparatus, this may frequently occur when the VCXO is used for clock recovery in a digital demodulator and the user is “channel surfing” (i.e., scanning channels). During such relatively high slew rate conditions, the VCXO may exhibit a distorted output signal wherein the output signal exhibits pulse asymmetry. In the worst case, for very high slew rates of the control voltage, the pulse asymmetry may be so severe as to result in missing pulses.
The VCXO symmetry problem, as recognized herein, comprises an aspect of the present invention and will be hereinafter referred to as the “PWM” (pulse width modulation) effect. This effect is illustrated in the diagram of
FIG. 2
for the conventional VCXO shown in FIG.
1
.
FIG. 2
illustrates bias voltage (Vbias) conditions for three time intervals (T
1
-T
2
, T
2
-T
3
and T
3
-T
4
) and the VCXO clock output signal (CL) symmetry for the three time intervals. Symmetry is illustrated by the three inset clock (CL) signal waveforms
202
for the period from T
1
to T
2
,
204
for the period from T
2
to T
3
and
206
for the period from T
3
to T
4
.
As shown, when the VCXO control voltage (Vbias) is of a constant (or slowly changing) value (intervals T
1
-T
2
and T
3
-T
4
), the clock output signal CL exhibits symmetry. Conversely, for rapidly changing values of Vbias (interval T
2
-T
3
) the clock output signal CL exhibits a distortion wherein the pulses are asymmetrical and some pulses may even be missing (as signified by the dotted line).
The present invention resides, in a first part, in the recognition of the PWM problem and in a second part, in providing a solution to the PWM problem that is both effective and economical.
Advantageously, the solution of the PWM effect, in accordance with the present invention, additionally provides the benefits of an extended tuning range and a reduced crystal power dissipation.
In accordance with the principles of the invention, circuit means are provided in the AC feedback path of a VCXO for effectively isolating the frequency control voltage (Vbias) from the input and the output terminals of the VCXO inverter.
In a preferred application of the principles of the invention the AC feedback path comprises a tank circuit including a crystal having a first plate coupled to an output of the inverter via a source resistance, coupled to a source of reference potential via a tuning means and coupled to a source of the bias voltage. The second plate of the crystal is coupled to an input of the inverter and coupled to the source of reference potential via a capacitor of fixed value. Also, the source resistance is of a relatively high value selected to substantially attenuate the bias voltage.


REFERENCES:
patent: 5113156 (1992-05-01), Mahabadi et al.
patent: 5844448 (1998-12-01), Jackoski et al.
patent: 6025757 (2000-02-01), Tsukagoshi et al.
patent: 6046648 (1998-12-01), Nakamiya et al.
patent: 58-111505 (1983-07-01), None

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