VCSEL having a self-aligned heat sink and method of making

Details VCSEL having a self-aligned heat sink and method of making VCSEL having a self-aligned heat sink and method of making

1995-03-17

1997-08-05

Kunemund, Robert

Semiconductor device manufacturing: process

Making device or circuit emissive of nonelectrical signal

Including integrally formed optical element

438 39, 438584, H01L 2120

Patent

active

056542283

ABSTRACT:
A substrate (102) having a surface (103) with a first stack of distributed Bragg reflectors (106), a first cladding region (107), an active region (108), a second cladding region (109), a second stack of distributed Bragg reflectors (110), and a contact region (111) is provided. A mesa (131) with a surface (133) and a trench (136) is formed. A first dielectric layer (122) is formed overlying substrate (102) and covering a portion of trench (136). A second dielectric layer (128) is formed on surface (133) of mesa (131). A seed layer (126) having a pattern is formed, with the pattern of seed layer (126) having an opening on a portion of second dielectric layer (128) of mesa (131). A metal is selectively plated on seed layer (126), thereby generating a layer (204) on seed layer (126) for removal of heat from VCSEL (101).

REFERENCES:
patent: 5206871 (1993-04-01), Deppe et al.
patent: 5316968 (1994-05-01), Choquette
patent: 5359447 (1994-10-01), Hahn et al.
patent: 5422901 (1995-06-01), Lebby et al.
patent: 5434940 (1995-07-01), Roff et al.
patent: 5482891 (1996-01-01), Shieh et al.

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