VCO power-up circuit for PLL and method thereof

Details VCO power-up circuit for PLL and method thereof VCO power-up circuit for PLL and method thereof

1993-10-28

1994-10-25

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 14, 331 17, 331 25, H03L 300, H03L 7093

Patent

active

053592972

ABSTRACT:
A power-on reset circuit controls a PLL to prevent overshoot of the VCO during power-up. The power-on reset circuit asserts a control signal upon detecting the power supply potential to the PLL below a predetermined threshold. The control signal enables a pull-down transistor to attenuate the control voltage to the VCO and reduce the output frequency of the VCO. The control signal further blocks the input reference signal to the phase detector. With the input reference signal blocked, the phase detector produces only down pulses to the charge pump during subsequent high to low logic transitions of the feedback signal from the VCO thereby further discharging the loop node and reducing the output frequency of the VCO. Following power-up, the control signal disables the pull-down transistor and allows the input reference signal to reach the phase detector whereby the PLL begins normal frequency acquisition and lock sequencing.

REFERENCES:
patent: 4743864 (1988-05-01), Nakagawa et al.
patent: 4970408 (1990-11-01), Hanke et al.
patent: 5208555 (1993-05-01), Graham et al.

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