VCO-mixer structure

Details VCO-mixer structure VCO-mixer structure

1998-07-24

2001-02-27

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific input to output function

Combining of plural signals

C327S355000, C327S356000, C327S113000, C455S333000

Reexamination Certificate

active

06194947

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to voltage controlled oscillator (VCO) and mixer, and more particularly, to multi-phase VCO and mixer.
2. Background of the Related Art
Presently, a radio frequency (RF) communications system has a variety of applications including PCS communication and IMT systems. As such, a CMOS chip integration of the system has been pursued to reduce the cost, size and power consumption.
Generally, the RF communication system is composed of RF front-end block and base-band digital signal processing (DSP) block. Currently, the base-band DSP block can be implemented with low cost and low power CMOS technology. However, the RF front-end cannot be implemented by CMOS technology due to fundamental limits in speed and noise characteristics, which are below the speed and noise specification of popular RF communication systems.
For example, the PCS hand-phone system operate at a frequency over 2.0 GHz, but current CMOS technology can support reliably operation only up to a frequency of 1.0 GHz in terms of speed and noise. Hence, the RF front-end block is implemented using bipolar or bi-CMOS technology that has better speed and noise characteristics than CMOS technology, but is more expensive and consumes more power.
One of the main causes for the 1 GHz limitation is the structure of the VCO and the mixer.
FIG. 1
is a circuit diagram of the VCO-mixer according to a background art. As shown in
FIG. 1
, the VCO
10
includes four differential delay cells
12
,
14
,
16
and
18
and has a structure similar to a ring oscillator. The four delay cells
12
-
18
are serially connected and generate a clock signal LO+ and an inverted clock signal LO−, each having a frequency of f
o
. A control circuit for the VCO
10
that generates a frequency control signal includes a phase frequency detector
4
, a charge pump
6
and a loop filter
8
that outputs the frequency control signal to each of the delay cells
12
-
18
. The phase frequency detector
4
receives a reference clock signal f
ref
and a VCO clock signal f
VCO
from a reference clock divider circuit
2
and a VCO clock divider circuit
3
, respectively. The frequency f
o
of the clock signals LO+ and LO− is represented by M/K (f
ref
)=f
o
. Thus, the frequency f
o
is based on the reference clock signal f
ref
and the divider circuits
2
and
3
.
The mixer
20
, such as Gilbert - Multiplier, multiplies the input signals, such as radio frequency (RF) signals RF+ and RF−, with the clock signals LO+ and LO−. The mixer
20
includes two load resistors R
1
and R
2
coupled to a source voltage V
DD
, eight NMOS transistors
21
-
28
, and a current source I
S1
. The gates of the NMOS transistors
21
and
22
are coupled to receive the clock signal LO+, and the gates of the NMOS transistors
23
and
24
are coupled to receive the inverted clock signal LO−. The gates of the NMOS transistors
25
and
26
receive a common bias voltage V
Bias
. The gates of the NMOS transistors
27
and
28
receive the RF signals RF+ and RF−, respectively. Therefore, the clock signals LO+ and LO− are multiplied with the RF signals RF+ and RF− only when the transistors
25
and
27
or the transistors
26
and
28
are turned on together. The output signals OUT+ and OUT− of the mixer
20
has a frequency lower than its original frequency by the frequency f
o
of the clock signals LO+, LO−.
As discussed above, a wide frequency range and a low phase noise are desirable for various applications. However, the VCO-mixer structure
10
and
20
can only support up to a frequency 1 GHz with reliable phase noise and frequency range. The performance of the VCO-mixer structure
10
and
20
becomes worse in terms of phase noise and frequency range and is unacceptable as the frequency of the clock signals LO+ and LO− from the VCO increases. Hence, the VCO
10
and the mixer
20
cannot be readily implemented when the frequency f
o
of the clock signals LO+ and LO− is over 1 GHz.
SUMMARY OF THE INVENTION
An object of the present invention is to at least substantially obviate problems and disadvantages of the related art.
A further object of the present invention is to fabricate a VCO-mixer on a single substrate.
Another object of the present invention is to increase the frequency range of a VCO-mixer structure.
Still another object of the present invention is to reduce the noise of a VCO-mixture structure.
Another object of the present invention is to increase a performance of the VCO-mixer structure.
To achieve the advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the structure of the invention comprises a clock generator for generating multi-phase clock signals having a first frequency lower than an original frequency, and a mixer for producing at least sequence of clock signals having the original frequency using the multi-phase clock signals and then multiplying the at least one sequence of clock signals with received RF signals.
In another aspect of the present invention, a method of operating a CMOS which has a clock generator and a mixer comprises the steps of generating multi-phase clock signals having a first frequency lower than an original frequency through the clock generator, producing at least one sequence of clock signals having the original frequency by combining the multi-phase clock signals, and multiplying the at least one sequence of clock signals with RF signals received to the CMOS through the mixer.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.


REFERENCES:
patent: 5418815 (1995-05-01), Ishikawa et al.
patent: 5438591 (1995-08-01), Oie et al.
patent: 5448772 (1995-09-01), Grandfield
patent: 5734970 (1998-03-01), Saito
patent: 5794119 (1998-08-01), Evans et al.

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