VCO gain self-calibration for low voltage phase lock-loop...

Details VCO gain self-calibration for low voltage phase lock-loop... VCO gain self-calibration for low voltage phase lock-loop...

2000-12-13

2003-04-22

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

C331S00100A, C331S017000, C331S175000, C331S17700V, C331S034000

Reexamination Certificate

active

06552618

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to electronics, and specifically to phase-lock loop circuits.
BACKGROUND OF THE INVENTION
A phase-lock loop (PLL) is a circuit that generates a periodic output signal having a constant phase relationship with respect to a periodic input signal. PLLs are widely used in many types of measurement, microprocessor, and communication applications. A typical PLL incorporates a voltage-controlled oscillator (VCO). A VCO is a device that generates a periodic output signal having a frequency that is a function of the VCO input voltage. VCOs are typically designed to operate over a wide range of application frequencies, and over a wide range of process and temperature variation. Of particular interest are the VCO operating characteristics of frequency range and gain.
In order to span a wide range of operating frequencies, a common practice is to increase VCO gain, K
O
. However, the larger the K
O
, the larger the sensitivity of the VCO to its input modulation noise, which includes charge pump noise, loop filter noise, and ripple noise. The ripple noise is due to the possible mismatching between the charge pump up and down currents and the charge sharing effect. PLL jitter can be reduced by decreasing the gain of the VCO, K
O
, while increasing the charge pump current at the same time, if charge pump up and down currents are well matched.
One approach of reducing K
O
while at the same time spanning a wide frequency range is to break a wide range tuning curve into a number of narrower, overlapping range sections as described in U.S. Pat. No. 5,942,949, issued to Wilson et al. However, in deep submicron processes, the VCO gain can have a relatively high dependence on the process due to the variation in resistor, capacitor and transistor threshold voltages. Based on a simulation, it has been shown that K
O
can vary over processing by a factor of 8:1. The variation is also greatly influenced by the VCO structure and targeted frequency range. The conventional center frequency auto-calibration scheme, as described in U.S. Pat. No. 5,942,949, fails to limit the variation of K
O
caused by the process variation and by the frequency range over which it operates. This K
O
variation problem may degrade the loop stability margin and jitter performance.
SUMMARY OF THE INVENTION
The present invention includes a process for calibrating gain of a voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) circuit. The VCO has a plurality of input voltage versus output frequency operating curves. The method includes a selecting one of the VCO operating curves and determining VCO gain using the selected operating curve. If the value of VCO gain is not within a predetermined range, the VCO gain is adjusted and the process of selecting an operating curve and determining VCO gain is repeated.
Another aspect of the present invention includes a PLL circuit having a VCO. The VCO receives a loop-filter voltage signal and provides a PLL output signal. The VCO also has a VCO gain and a VCO center frequency which are automatically calibrated during a calibration phase.


REFERENCES:
patent: 5382922 (1995-01-01), Gersbach et al.
patent: 5942949 (1999-08-01), Wilson et al.
patent: 6114920 (2000-09-01), Moon et al.

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