VCO circuit with wide output frequency range and PLL circuit...

Details VCO circuit with wide output frequency range and PLL circuit... VCO circuit with wide output frequency range and PLL circuit...

2001-06-21

2003-09-09

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

C331S074000, C331S034000

Reexamination Certificate

active

06617933

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage-controlled oscillating circuit, and more particularly, to a voltage-controlled oscillating circuit capable of altering an oscillating frequency according to a control voltage and to a phase-locked loop circuit, a so-called PLL circuit, equipped with the voltage-controlled oscillating circuit.
2. Description of the Background Art
In order to cooperatively operate a plurality of internal circuits implemented on the same system, employed are phase-locked loop circuits (PLL circuit) each generating a synchronized clock. Especially, in recent years, an LSI (Large Scale Integrated Circuit) has experienced progress toward its higher speed operation in company with miniaturization; as a result, a margin in phase shift between a clock of the entire system on which an LSI is implemented and an internal clock of the LSI has become narrowed, which in turn, has enhanced a chance of usage of a PLL circuit to compensate a phase shift.
As a result, many of PLL circuits are required to be incorporated, which leads to increase in design load in order to output synchronized clocks corresponding to a wide frequency range. Accordingly, it is important to make an output frequency range (lock range) of a PLL circuit as wide as possible and thereby, cover a necessary frequency range with a single PLL circuit.
Since a lock range of a PLL circuit is largely dependent on an output frequency range of a voltage-controlled oscillator included, it is important to ensure a wide output frequency range of the voltage-controlled oscillating circuit. A general configuration of such a voltage-controlled oscillating circuit is shown, for example in
FIG. 2
of Japanese Patent Laying-Open No. 9-200001(1997). The general configuration of a voltage-controlled oscillating circuit disclosed in the publication is hereinafter referred to the prior art.
FIG. 12
is a circuit diagram representing a configuration of the prior art voltage-controlled oscillating circuit
70
.
Referring to
FIG. 12
, the voltage-controlled oscillating circuit
70
has a ring oscillator constructed from inverters at three stages. The ring oscillator includes: an inverter formed of a P-channel transistor
51
a
and an N-channel transistor
51
b;
an inverter formed of a P-channel transistor
52
a
and an N-channel transistor
52
b;
and an inverter formed of a P-channel transistor
53
a
and an N-channel transistor
53
b.
Capacitors
51
c,
52
c
and
53
c
to determine a delay value of the ring oscillator are coupled with output nodes of the respective inverters.
The voltage-controlled oscillating circuit
70
includes: a P-channel transistor
54
receiving a fixed voltage Vf at the gate thereof; a P-channel transistor
55
receiving a control voltage Vc at the gate thereof; and N-channel transistors
56
and
57
constituting a current mirror circuit.
The voltage-controlled oscillating circuit
70
further includes: P-channel transistors
59
,
60
and
61
each, coupled between a corresponding one of the inverters at three stages and a power source node supplying a power source voltage Vdd, and for controlling operating currents supplied to the respective inverters; and a transistor
58
constituting a current mirror circuit together with the transistor
59
.
The voltage-controlled oscillating circuit
70
still further includes: N-channel transistors
62
,
63
and
64
each, coupled between a corresponding one of ground nodes supplying a ground voltage Vss and a corresponding one of the inverters.
In the voltage-controlled oscillating circuit
70
, the ring oscillator constituted of the inverters at three stages performs an oscillating operation. An oscillating frequency of the ring oscillator is determined in the following way.
Into the transistor
56
, there flows the sum of a current flowing between the drain and source of the transistor
54
receiving the fixed voltage Vf at the gate thereof and a current flowing between the drain and source of the transistor
55
receiving the control voltage Vc at the gate thereof. The current flowing between the drain and source of the transistor
55
is controlled by the controlled voltage Vc.
Since the transistors
56
and
57
constitute a current mirror circuit, currents equal to each other flow through the respective transistors
56
and
57
and the current of the transistor
57
flows through the transistor
58
. Since the transistors
58
and
59
constitute a current mirror circuit, duplicated current flows through the transistor
59
. Furthermore, into the P-channel transistors
60
and
61
for current controlling, there flow currents proportional to respective size ratios of the transistors
60
and
61
to the transistor
59
(or the transistor
58
). Likewise, into the N-channel transistors
62
,
63
and
64
for current controlling, there flow currents proportional to respective size ratios of the transistors
62
,
63
and
64
to the transistor
57
(or the transistor
56
).
In such a configuration, an oscillating frequency is determined by operating currents flowing through the respective inverters at three stages constituting the ring oscillator and values of the delay capacitors
51
c,
52
c
and
53
c.
The capacitors
51
c,
52
c
and
53
c
determine delay times at the respective stages as load capacitances of the respective inverters constituting the ring oscillator.
Hence, an oscillating frequency of the voltage-controlled oscillating circuit
70
is altered by changing the control voltage Vc inputted to the gate of the transistor
55
to change each of operating currents flowing through the respective inverters constituting the ring oscillator. Furthermore, since operating currents flowing through the respective inverters of the ring oscillator are also altered by changing a set value of the fixed voltage Vf inputted to the transistor
54
; therefore, an oscillating frequency differs under the same control voltage Vc applied. In other words, obtained are a plurality of oscillating frequency vs. control voltage Vc characteristics with a fixed voltage Vf as a parameter.
However, the prior art voltage-controlled oscillating circuit
70
determines operating currents for the respective inverters constituting the ring oscillator through voltage to current conversion according to the inputted control voltage Vc. As a result, a clock CLKO having an oscillating frequency corresponding to operating currents of the inverters is outputted from the ring oscillator.
Therefore, since a configuration is adopted of controlling an oscillating operation of the ring oscillator by a current value, it is difficult to broaden an oscillating frequency range. For this reason, it is also difficult to realize a PLL with a wide lock range even if a PLL circuit is constructed using such as voltage-controlled oscillating circuit.
Moreover, as a typical cause for jitter (phase deviation) occurring in a clock generated by the PLL circuit, there can be named noise on a power source voltage pulse (hereinafter simply referred to as power source noise).
At this point, referring again to
FIG. 12
, when noise occurs in the power source voltage Vdd supplied by the power source node, source voltages of the current control P-channel transistors
58
,
59
,
60
and
61
are directly varied; therefore, an influence of the power source noise is directly exerted on operating currents for the inverters constituting the ring oscillator, with the result that an oscillating frequency of the voltage-controlled oscillating circuit
70
is also affected directly by the power source noise.
Therefore, a regulator circuit or a filter circuit for reducing power source noise was required for use of the prior art voltage control oscillating circuit
70
.
FIG. 13
is a circuit diagram representing a configuration of a filter circuit provided correspondingly to a power source voltage of the voltage-controlled oscillating circuit
70
.
Referring to
FIG. 13
, a filter circuit
71
includes: a smoothing capacitance
72
coupled betwee

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