VCDL with linear delay characteristics and differential...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform

Reexamination Certificate

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C327S158000

Reexamination Certificate

active

06844766

ABSTRACT:
A voltage-controlled delay line (VCDL) comprises a series of delay cells outputting a clock output signal having a delay relative to a clock input signal input to the series of delay cells. A duty-cycle correction section corrects the duty cycle of the clock output signal by providing opposite current outputs which are fed back to the series of delay cells to substantially simultaneously charge and discharge current of the series of delay cells in opposite directions. A control current input to the series of delay cells controls the amount of the delay. A voltage-to-current converter converts a control voltage into the control current so that the delay changes substantially linearly as the control voltage changes. The method for using the VCDL to produce linear delay is also included. The VCDL can be used in a delay-locked loop (DLL).

REFERENCES:
patent: 5012142 (1991-04-01), Sonntag
patent: 5231320 (1993-07-01), Kase
patent: 5559476 (1996-09-01), Zhang et al.
patent: 5757873 (1998-05-01), Hunt
patent: 6081146 (2000-06-01), Shiochi et al.
patent: 6411145 (2002-06-01), Kueng et al.
patent: 6703879 (2004-03-01), Okuda et al.
CMOS Low-Voltage Rail-To-Rail V-I Convertor, Chung-Chih Hung, Changku Hwang, and Mohammed Ismail, 1999 IEEE, pp. 1337 through 1340.
An Integrated High Resolution CMOS Timing Generator Based On An Array of Delay Locked Loops, Jorgen Christiansen, 1996 IEEE.

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