Vcc independent time delay circuit

Details Vcc independent time delay circuit Vcc independent time delay circuit

2001-03-28

2003-09-16

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S276000, C327S288000, C326S034000

Reexamination Certificate

active

06621320

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to logic circuits and more specifically to time delay logic circuits and oscillators.
BACKGROUND OF THE INVENTION
There are many types of prior art time delay circuits. Often, time delay circuits included an analog time delay such as a resistive-capacitive (RC) circuit. An RC circuit receives a pulse and then delays or extends that pulse according to an RC time constant of the RC circuit.
FIG. 1
shows a RC time delay circuit
100
. A short pulse
102
is received in the input terminal
104
through a gating circuit
106
. The gating circuit applies the input pulse to the input of the RC tank circuit
108
. The RC tank circuit includes resistor
109
and capacitor
110
. An extended pulse
120
is output from the RC tank circuit through an output gate
130
. The extended pulse is extended according to the RC time constant of the tank circuit. The RC time delay circuit
100
has several shortfalls. One shortfall is that it is extremely dependent upon temperature and the corresponding variation of the resistance and the capacitance of the resistor
109
and capacitor
110
, respectively. The dependence on temperature results in an extremely variable time delay. Another Shortfall of the RC time delay is that the RC time constant is also dependent upon the applied voltage, Vcc. Because the output of the RC time delay circuit is variable, then it is not precisely predictable or reliable unless the temperature of the resistor
109
and the capacitor
110
is also known. If the temperature of the resistor
109
and the capacitor
110
is also known, then the resulting time delay can be correlated to temperature and thereby predicted. Unfortunately, monitoring the temperature of R
1
and C
1
requires a more complicated circuit.
A resistive circuit can also be used in a bias current controlled oscillator
200
as shown in FIG.
2
. Resistor
202
and transistor M
1
set up a bias current for transistors M
2
and M
3
. Transistors M
2
and M
3
create reference voltages REF
P
and REF
N
, respectively. REF
P
and REF
N
are input to an oscillator
210
that includes biasing transistors M
4
, M
5
, and three oscillator stages
212
,
214
,
216
. Additional stages could also be included but the illustration is limited to the three stages for simplicity of discussion. The first oscillator stage
212
includes transistors M
6
, M
7
. The second oscillator stage
214
includes transistors M
8
, M
9
. The third oscillator stage
216
includes transistors M
10
, M
11
. Reference voltages REF
P
and REF
N
are used to bias the three stages
212
,
214
,
216
of the oscillator
210
. Each of the stages
212
,
214
,
216
are delay inverters. The input to the stages
212
,
214
,
216
are linked to the output of the stages to create an oscillator. The oscillation frequency of the bias current controlled oscillator
200
is dependent upon the voltage drop across the biasing resistor
202
. The voltage drop across the resistor
202
varies with the temperature of the resistor
202
or the current flow through the resistor
202
. The oscillation frequency of the bias current controlled oscillator
200
is also dependent on variations in the Vcc input voltage. Further, the bias current controlled oscillator
200
also sinks a static current through the resistor
202
and the first stage
212
, even when the oscillator is not oscillating.
For one embodiment of the invention, a time delay circuit comprises a first transistor and a delay element. An input voltage is applied between the gate and the drain of the first transistor. An output voltage is taken at the source of the first transistor. The output voltage of the first transistor is coupled to the delay element, biasing the delay element.


REFERENCES:
patent: 4578600 (1986-03-01), Magee
patent: 4945262 (1990-07-01), Piasecki
patent: 5051630 (1991-09-01), Kogan et al.
patent: 5453709 (1995-09-01), Tanimoto et al.
patent: 5748542 (1998-05-01), Zheng et al.
patent: 5786255 (1998-07-01), Yeh et al.
patent: 6041089 (2000-03-01), Yokomizo
patent: 6184090 (2001-02-01), Lin

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