Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-06-03
2004-09-21
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
Reexamination Certificate
active
06794299
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to various methods of controlling conformal film deposition processes, and a system for accomplishing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
Typically, integrated circuit devices are comprised of hundreds or millions of transistors formed above a semiconducting substrate. By way of background, an illustrative field effect transistor
10
, as shown in
FIG. 1
, may be formed above a surface
15
of a semiconducting substrate or wafer
11
comprised of doped-silicon. The substrate
11
may be doped with either N-type or P-type dopant materials. The transistor
10
may have a doped polycrystalline silicon (polysilicon) gate electrode
14
formed above a gate insulation layer
16
. The gate electrode
14
and the gate insulation layer
16
may be separated from doped source/drain regions
22
of the transistor
10
by a dielectric sidewall spacer
20
. The source/drain regions
22
for the transistor
10
may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate
11
. Shallow trench isolation regions
18
may be provided to isolate the transistor
10
electrically from neighboring semiconductor devices, such as other transistors (not shown). Additionally, although not depicted in
FIG. 1
, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate
11
.
The gate electrode
14
has a critical dimension
12
, i.e., the width of the gate electrode
14
, that approximately corresponds to the channel length
13
of the device when the transistor
10
is operational. Of course, the critical dimension
12
of the gate electrode
14
is but one example of a feature that must be formed very accurately in modern semiconductor manufacturing operations. Other examples include, but are not limited to, conductive lines, openings in insulating layers to allow subsequent formation of a conductive interconnection, i.e., a conductive line or contact, therein, etc.
During the course of manufacturing integrated circuit devices, various conformal films or process layers are deposited above various features that have previously been formed on the wafer
11
. For example, in the case where a plurality of gate electrode features have been formed, a layer of insulating material, e.g., silicon dioxide, silicon oxynitride, silicon nitride, etc., may be conformally deposited above and around the gate electrode features as part of the process of forming sidewall spacers
20
adjacent the gate electrode structures
14
. Ideally, the conformally deposited layer of material will uniformly cover the top surface
14
A and sidewall surfaces
14
B of the gate electrode structures
14
. Moreover, such conformally deposited layers or films should avoid excessive thickness variations and not lead to the formation of voids in the completed structure. It should be understood that, by use of the term conformal to describe the deposited layer, it is only intended to mean that the layer is deposited so as to cover substantially all of the surfaces of the features. Such a conformal layer may exhibit undesirable thickness variations, voids, non-uniformities, or other types of defects.
As another example, in the situation where a plurality of openings or trenches are formed in a process layer or substrate, one or more layers of materials may be conformally deposited in these trench or opening type features. For example, in the case where conductive interconnections comprised of copper are formed on an integrated circuit device, the process flow may involve the conformal deposition of a relatively thin barrier metal layer, e.g., tantalum, and a copper seed layer in an opening formed in a layer of insulating material. Layers of material may also be conformally deposited in trenches formed in the semiconducting ducting substrate.
Unfortunately, in some cases, the conformally deposited layer of material does not exhibit some of the desirable characteristics outlined above. For example, a layer of silicon dioxide formed above a plurality of gate electrode structures
14
may exhibit poor coverage of the sidewalls
14
B of the gate electrodes
14
. Alternatively, the thickness of the layer of silicon dioxide may be much less above the top surface
14
A of the gate electrode
14
as compared to the thickness of the layer of silicon dioxide on the sidewalls
14
B of the gate electrode
14
and/or between adjacent gate electrode structures
14
. Conformally deposited films or layers in openings or trench type features, e.g., a barrier metal layer, may also exhibit poor sidewall coverage, excessive variations and/or non-uniformities in the thickness of the deposited layer on the sidewalls and bottom of the opening, and, in a more severe example, tend to “pinch-off” the openings near the top of the opening, thereby tending to create an undesirable void in the opening or excessive interconnect resistance, etc.
Such problems encountered in accurately forming conformally deposited films or layers may lead to problems with device manufacturing and/or performance. For example, inability to control the thickness and/or sidewall coverage of a conformally deposited layer or film may lead to problems in controlling the thickness and/or coverage of sidewall spacers
20
formed adjacent a gate electrode structure
14
. In turn, this may adversely impact device performance, at least to some degree, as various implant processes, i.e., a source/drain implant process, may be performed after the sidewall spacers
20
are formed. If the sidewall spacers
20
are not as thick as intended by the product design, due to poor thickness control and/or poor sidewall coverage, then the source/drain implant may be located at a position that is different than that anticipated in the design of the product. As another example, if a conformally deposited barrier metal layer and/or copper seed layer exhibits poor thickness control and/or excessive thickness variations, the resulting conductive interconnection may not exhibit the desired electrical characteristics, e.g., voids may be formed in the conductive interconnection.
There may be a variety of causes for the problems encountered in forming conformally deposited films above a plurality of features, e.g., gate electrodes, openings in insulating layers, etc. For example, there may be problems with the process recipes used in forming such layers. Additionally, variations in the critical dimensions and/or profile of the various features from those anticipated in the product design may also cause one or more of the types of problems described above.
The present invention is directed to a method and system that may solve, or at least reduce, some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
The present invention is generally dir
Bennett David
Markle Richard J.
Advanced Micro Devices , Inc.
Niebling John F.
Stevenson André C
Williams Morgan & Amerson
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