Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with field effect transistor
Reexamination Certificate
2002-10-01
2004-11-09
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Combined with field effect transistor
C257S124000
Reexamination Certificate
active
06815734
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed to semiconductor devices and, more specifically, to semiconductor devices including thyristors and implementations thereof including memory, current-switching applications and others.
BACKGROUND
An important part in the design, construction, and manufacture of semiconductor devices concerns semiconductor memory and other circuitry used to store information. Conventional random access memory devices include a variety of circuits, such as SRAM and DRAM circuits. The construction and formation of such memory circuitry typically involves forming at least one storage element and circuitry designed to access the stored information. DRAM is very common due to its high density (e.g., high density has benefits including low price), with DRAM cell size being typically between 6 F
2
and 8 F
2
, where F is the minimum feature size. However, with typical DRAM access times of approximately 50 nSec, DRAM is relatively slow compared to typical microprocessor speeds and requires refresh. SRAM is another common semiconductor memory that is much faster than DRAM and, in some instances, is of an order of magnitude faster than DRAM. Also, unlike DRAM, SRAM does not require refresh. SRAM cells are typically constructed using 4 transistors and 2 resistors or 6 transistors, which result in much lower density and is typically between about 60 F
2
and 100 F
2
.
Various SRAM cell designs based on a NDR (Negative Differential Resistance) construction have been introduced, ranging from a simple bipolar transistor to complicated quantum-effect devices. These cell designs usually consist of at least two active elements, including an NDR device. In view of size considerations, the construction of the NDR device is important to the overall performance of this type of SRAM cell. One advantage of the NDR-based cell is the potential of having a cell area smaller than four-transistor and six-transistor SRAM cells because of the smaller number of active devices and interconnections.
Conventional NDR-based SRAM cells, however, have many problems that have prohibited their use in commercial SRAM products. These problems include, among others: high standby power consumption due to the large current needed in one or both of the stable states of the cell; excessively high or excessively low voltage levels needed for cell operation; stable states that are too sensitive to manufacturing variations and provide poor noise-margins; limitations in access speed due to slow switching from one state to the other; limitations in operability due to temperature, noise, voltage and/or light stability; and manufacturability and yield issues due to complicated fabrication processing.
Thyristor-type NDR devices can be effective in overcoming many previously unresolved problems for thyristor-based applications as well as memory applications. An important consideration in the design of a capacitively-coupled thyristor device involves designing the body of the thyristor sufficiently thin, so that the capacitive coupling between the control port and the thyristor base region can substantially modulate the potential of the base region. Another important consideration in semiconductor device design, including those employing thin capacitively-coupled thyristor-type devices, includes forming devices in highly dense applications. For instance, it may be advantageous to form a vertical thyristor having a cathode emitter region buried in a semiconductor substrate below one or more other thyristor regions. However, it is sometimes difficult to implement such a vertically-arranged thyristor in highly dense implementations due to difficulties associated with isolating the buried emitter region and other regions from other adjacent circuitry (e.g., from other emitter regions) in the substrate.
These and other design considerations have presented challenges to implement such a thin capacitively-coupled thyristor in a variety of circuit implementations, and in particular to highly dense applications.
SUMMARY
The present invention is directed to overcoming the above-mentioned challenges and others related to the types of devices and applications discussed above and in other applications, including memory cells and other switching circuits. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a semiconductor device is manufactured having a trench with a shallower portion and a deeper portion in a substrate, the deeper portion being arranged to electrically insulate a buried emitter region of a thyristor. The thyristor includes a body and a control port, the body having an emitter region at a bottom portion of the thyristor and buried in the substrate. The control port is arranged to capacitively couple to the body for controlling current flow in the thyristor. Using a varied trench depth to electrically insulate a buried emitter in this manner is particularly useful, for example, in memory and/or other applications employing cathode-down thyristors and in high-density applications where it is desirable to electrically insulate buried emitter regions and/or other circuit regions from nearby circuitry.
In one implementation, the semiconductor device further includes a pass device electrically coupled to the buried emitter region of the thyristor. Source/drain regions of the pass device are formed separated by a channel region in the substrate, and a gate is formed over the channel region and adapted for capacitively coupling thereto for controlling current in the pass device. The pass device is adapted for controlling access between the buried emitter region and a data output node, such as a bit line.
In another example embodiment of the present invention, the first, relatively deeper portion of the trench is further adapted for inhibiting diffusion in the substrate. For instance, when emitter regions of thyristors are formed, dopants used to form the emitter regions can out diffuse or otherwise reach other portions of the substrate, which can be undesirable. With this approach, such undesirable diffusion can be inhibited or even eliminated.
In a more particular example embodiment of the present invention, one or more of the semiconductor devices discussed above are formed in a memory array and adapted for read and write access. A buried emitter region of each thyristor is adapted for storing data (e.g., a “one” or a “zero”) as a function of its state (e.g., controlled by the latched state of the thyristor). The memory cell is arranged such that the storage and retrieval of the data can be controlled via signals applied to the thyristor control port and the gate of the pass device, as well as to emitter regions of the thyristor. Electrical insulation of the buried emitter regions is achieved using the varied-depth trench, facilitating the formation of highly dense arrays of thyristor-based memory cells.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.
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Horch Andrew
Robins Scott
Pham Long
Pizarro-Crespo Marcos D.
T-Ram, Inc.
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