Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Patent
1997-07-02
2000-12-12
Graybill, David E.
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
438118, H01R 2500
Patent
active
061597643
ABSTRACT:
An integrated circuit (IC) package includes a transfer molded plastic or preformed ceramic package body, having an IC die positioned therein. A peripheral lead, Leads-Over-Chip (LOC), or Leads-Under-Chip (LUC) lead frame, includes a plurality of leads with portions enclosed within the package body that electrically connect to the IC die. A heat sink is positioned at least partially within the package body so a surface of a first portion of the heat sink faces the lead frame in close proximity to a substantial part, at least eighty percent, of the area of the enclosed portion of the lead frame to thereby substantially reduce an inductance associated with each of the leads. The heat sink is preferably grounded so it acts as a ground plane for the leads, but it may also be electrically isolated from the lead frame, or connected to a signal voltage. A die-attach area on the surface of the first portion of the heat sink is attached to the IC die, and a second portion of the heat sink is connected to the first portion substantially opposite the die-attach area and projects away from the first portion and the IC die to dissipate heat from the IC die.
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Brooks Jerry M.
Kinsman Larry D.
Graybill David E.
Micro)n Technology, Inc.
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