Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2000-03-30
2003-01-14
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S112000, C438S123000, C257S675000
Reexamination Certificate
active
06506629
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to devices and methods for reducing lead inductance in integrated circuit (IC) packages and, more specifically, to heat sinks for reducing lead inductance in such packages, minimizing volume of heat sink material, enhancing retention of the heat sink in molded packages, and improving moldability of the package encapsulant.
2. State of the Art
Integrated circuit (IC) packages typically contain small, generally rectangular integrated circuits referred to as IC “dice” or “chips.” These IC dice come in an almost infinite variety of forms, including, for example, Dynamic Random Access Memory (DRAM) dice, Static Random Access Memory (SRAM) dice, Synchronous DRAM (SDRAM) dice, Sequential Graphics Random Access Memory (SGRAM) dice, flash Electrically Erasable Programmable Read-Only Memory (EEPROM) dice, and processor dice.
Packaged IC dice communicate with circuitry external to their packages through lead frames embedded in the packages. These lead frames generally include an assembly of leads that extend into the packages to connect to bond pads on the IC dice through thin wire bonds or other connecting means and extend from the packages to terminate in pins or other terminals that connect to the external circuitry. Exemplary conventional lead frames include paddle-type wire-bond lead frames, which include a central die support and leads which extend to the perimeter of IC dice and connect to the dice through thin wire bonds, Leads-Over-Chip (LOC) lead frames, having leads which extend over an IC die to attach to and support the die while being electrically connected to the die through wire bonds or other connecting means, and Leads-Under-Chip (LUC) lead frames, having leads which extend under an IC die to attach to and support the die from below while being connected to the die typically through wire bonds.
As with all conductors, the leads in lead frames have an inductance associated with them that increases as the frequency of signals passing through the leads increases. This lead inductance is the result of two interactions: the interaction among magnetic fields created by signal currents flowing to and from an IC die through the leads (known as “mutual” inductance); and the interaction between the magnetic fields created by the signal currents flowing to and from the IC die through the leads and magnetic fields created by oppositely directed currents flowing to and from ground (known as “self” inductance).
While lead inductance in IC packages has not traditionally been troublesome because traditionally slow signal frequencies have made the inductance relatively insignificant, the ever-increasing signal frequencies of state of the art electronic systems have made lead inductance in IC packages significant. For example, overall performance of IC dice attached to leads in IC packages is slower than desirable because the inductance associated with the leads slows changes in signal current through the leads, causing signals to take longer to propagate through the leads. Also, digital signals propagating along the leads are dispersing (i.e., “spreading out”) because the so-called “Fourier” components of various frequencies that make up the digital signals propagate through the inductance associated with the leads at different speeds, causing the components, and hence the digital signals themselves, to disperse along the leads. While mild dispersion merely widens the digital signals without detrimental effect, severe dispersion can make the digital signals unrecognizable upon receipt. In addition, so-called “reflection” signals propagating along the leads as a result of impedance mismatches between the leads and IC dice or the leads and external circuitry caused, in part, by the inductance associated with the leads can distort normal signals propagating along the leads at the same time as the reflection signals. Further, magnetic fields created by signal currents propagating through the inductance associated with the leads can induce currents in nearby leads, causing so-called “crosstalk” noise on the nearby leads. While these various effects can be troublesome in any electronic system, the modern trend toward 3.3 volt systems and away from 5.0 volt systems only serves to make these effects more noticeable and significant.
Prior IC packages have been configured in an attempt to reduce various effects of lead inductance as described above. For example, U.S. Pat. No. 5,214,845, assigned to the assignee of the present invention, employs a flexible, laminated sandwich assembly of an outer ground plane and an outer power plane dielectrically isolated from a series of conductive traces running therebetween. The traces and planes are connected to corresponding bond pads on an IC die at one end, and to leads on the other, as by thermocompression bonding (in the case of a TAB embodiment), or by wire bonds. Such an arrangement obviously doubles the number of required I/O connections by requiring two connections for each lead, and thus necessitates additional assembly time and increases the possibility of a faulty connection. Further, the flexible sandwich assembly constitutes an additional element of the package, increasing material cost.
Another approach to reducing the inductance effects described above is disclosed in U.S. Pat. No. 5,559,306, in which metal plates are employed above and below leads extending to the exterior of plastic and ceramic packages to effect reduction of self and mutual inductance. However, such configurations as disclosed appear to require relatively complex fabrication techniques to locate and fix the plates relative to the die and lead fingers or other conductors for subsequent transfer molding of a filled-polymer package thereabout, while the ceramic package embodiment is not cost-effective for high-volume, commercial packaging.
Accordingly, the inventors have recognized the need for a low-cost, reduced-inductance IC package configuration adaptable to current packaging designs and employing conventional and readily-available materials, equipment and fabrication techniques.
SUMMARY OF THE INVENTION
An inventive integrated circuit (IC) package includes a package body, such as an extruded plastic or ceramic package body, having an IC die positioned therein. The IC die may be, for example, a Dynamic Random Access Memory (DRAM) die, a Static Random Access Memory (SRAM) die, a Synchronous DRAM (SDRAM) die, a Sequential Graphics Random Access Memory (SGRAM) die, a flash Electrically Erasable Programmable Read-Only Memory (EEPROM) die, or a processor die.
A lead frame, such as a conventional peripheral lead, Leads-Over-Chip (LOC), or Leads-Under-Chip (LUC) lead frame, includes a plurality of leads with portions enclosed within the package body that connect to the IC die. A heat sink is positioned at least partially within the package body so a surface of a first portion of the heat sink faces the lead frame in close proximity to a substantial part, such as at least 80 percent, of the enclosed portion of each of the leads of the lead frame to thereby substantially reduce an inductance associated with each of the leads. The heat sink is preferably grounded so it acts as a ground plane for the leads, but it may also be electrically isolated, connected to a signal voltage, or connected to a reference voltage other than ground. A die-attach area on the surface of the first portion of the heat sink provides a support for the IC die, and a second portion of the heat sink is connected to the first portion substantially opposite the die-attach area and projects away from the first portion and the IC die to dissipate heat from the IC die.
The inventors have thus provided a low-cost, reduced-inductance IC package configuration adaptable to current packaging designs and employing conventional and readily-available materials, equipment and fabrication techniques.
Another embodiment of the present invention is directed toward the heat sink of the previously summarized embodiment. Still anothe
Brooks Jerry M.
Kinsman Larry D.
Berezny Nema
Micro)n Technology, Inc.
Nguyen Tuan H.
TraskBritt
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