Variation reduction technique for charge pump transistor aging

Details Variation reduction technique for charge pump transistor aging Variation reduction technique for charge pump transistor aging

2003-01-23

2004-11-02

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S148000

Reexamination Certificate

active

06812755

ABSTRACT:

BACKGROUND OF INVENTION
As shown in
FIG. 1
, a typical computer system (
10
) has, among other components, a microprocessor (
12
), one or more forms of memory (
14
), integrated circuits (
16
,
17
) having specific functionalities, and peripheral computer resources (not shown), e.g., monitor, keyboard, software programs, etc. These components communicate with one another via communication paths (
19
), e.g., wires, buses, etc., to accomplish the various tasks of the computer system (
10
).
In order to properly accomplish such tasks, the computer system (
10
) relies on the basis of time to coordinate its various operations. To that end, a crystal oscillator (
18
) generates a system clock signal (referred to and known in the art as “reference clock” and shown in
FIG. 1
as SYS_CLK) to various parts of the computer system (
10
). Modern microprocessors and other integrated circuits, however, are typically capable of operating at frequencies significantly higher than the system clock signal, and thus, it becomes important to ensure that operations involving the microprocessor (
12
) and the other components of the computer system (
10
) use a proper and accurate reference of time.
One component used within the computer system (
10
) to ensure a proper reference of time among the system clock signal and a microprocessor clock signal, i.e., “chip clock signal” or CHIP_CLK, is a type of clock generator known as a phase locked loop (PLL) (
20
). The PLL (
20
) is an electronic circuit that controls an oscillator such that the oscillator maintains a constant phase relative to the system clock signal. Referring to
FIG. 1
, the PLL (
20
) has as its input the system clock signal, which is its reference signal, and outputs a chip clock signal (shown in
FIG. 1
as CHIP_CLK) to the microprocessor (
12
). The system clock signal and chip clock signal have a specific phase and frequency relationship controlled by the PLL (
20
). This relationship between the phases and frequencies of the system clock signal and chip clock signal ensures that the various components within the microprocessor (
12
) use a controlled and accounted for reference of time. When this relationship is not maintained by the PLL (
20
), however, the operations within the computer system (
10
) become non-deterministic.
Another component used within the computer system (
10
) to ensure a proper reference of time among the system clock signal and a microprocessor clock signal, i.e., “clock out signal” or CLK_OUT, is a type of clock generator known as a delay locked loop (DLL) (
22
). As the frequencies of modern computers continue to increase, the need to rapidly transmit data between chip interfaces also increases. To accurately receive data, a clock signal is often sent to help recover the data. The clock signal determines when the data should be sampled or latched by a receiver circuit.
The clock signal may transition at the beginning of the time the data is valid. The receiver circuit, however, may require that the clock signal transition during the middle of the time the data is valid. Also, the transmission of the clock signal may degrade as it travels from its transmission point. In both circumstances, a delay locked loop (
22
), or “DLL,” may be used to regenerate a copy of the clock signal at a fixed phase shift with respect to the original clock signal.
In
FIG. 1
, data is transmitted from integrated circuit (
17
) to the microprocessor (
12
). To aid in the recovery of the transmitted data, a clock signal (
21
) is also transmitted with the data. The microprocessor (
12
) may also transmit data to the integrated circuit (
17
) using an additional clock signal (not shown). The clock signal (
21
) may transition from one state to another at the beginning of data transmission. The microprocessor (
12
) requires a clock signal temporally located some time after the beginning of the valid data. Furthermore, the clock signal (
21
) may have degraded during transmission. The DLL (
22
) has the ability to regenerate the clock signal (
21
) to a valid state and to create a phase shifted version of the clock signal (
21
) to be used by other circuits. For example, the microprocessor (
12
) may use the phase shifted version of the clock signal (
21
) as the receiver circuit's sampling signal. The receiver circuit's sampling signal determines when the input to the receiver circuit should be sampled. The performance of a DLL (
22
) is critical and must maintain a proper reference of time on the CPU, or generically, an integrated circuit.
Circuit elements in a microprocessor (
12
), and more generally, an IC (
16
,
17
), continue to get smaller. Accordingly, more and more circuit elements may be packed into an IC (
16
,
17
). In
FIG. 2
, a cross sectional diagram of a particular type of circuit element, a p-channel transistor (
200
), is shown. The p-channel transistor (
200
) includes two n+ regions (
204
,
206
) implanted in a p-substrate (
210
) or a p-well. The two n+ regions (
204
,
206
) form a drain and source region for the p-channel transistor (
200
). The depth of the drain and source regions may determine a junction (
209
) thickness for current to flow from one n+ region (
204
or
206
), through a channel formed below a gate (
202
) when the transistor (
200
) is “on,” to the other n+ region (
206
or
204
). A source contact (
212
) and drain contact (
214
) allow a connection with the n+ regions (
204
,
206
), respectively. The p-channel transistor (
200
) is separated from other devices by a field oxide (
230
,
232
).
The p-channel transistor (
200
) is controlled by a voltage potential on a gate (
202
). A gate contact (
216
) allows a connection with the gate (
202
). The gate (
202
) is separated from the p-substrate (
210
) by a gate oxide (
208
).
A voltage potential difference between the source contact (
212
) and drain contact (
214
) is denoted V
ds
. A voltage potential difference between the gate contact (
216
) and the source contact (
212
) is denoted V
gs
. The voltage potential to turn the p-channel transistor (
200
) “on,” i.e., allow the p-channel transistor (
200
) to conduct current, is a threshold voltage potential denoted V
t
.
FIG. 3
shows a diagram of a current-voltage characteristic for a typical metal-oxide transistor. As shown in
FIG. 3
, the p-channel transistor (
200
shown in
FIG. 2
) is “off” when |V
gs
|<|V
t
| (
255
). The p-channel transistor (
200
shown in
FIG. 2
) is “on” and in a linear region of operation when |V
ds
|≦|V
gs
|−V
t
| and |V
gs
|≧|V
t
| (
265
). The p-channel transistor (
200
shown in
FIG. 2
) is “on” and in a saturation region of operation when |V
ds
|>|V
gs−V
t
| and |V
gs
≧|V
t
| (
275
).
As circuit elements in an IC (
16
,
17
shown in
FIG. 1
) continue to get smaller, features of the circuit elements, e.g., the gate oxide thickness, the depth of the two n+ regions (
204
,
206
shown in FIG.
2
), the spacing between the two n+regions (
204
,
206
shown in FIG.
2
), etc., get smaller.
SUMMARY OF INVENTION
According to one aspect of the present invention, an integrated circuit comprises a charge pump arranged to generate a current dependent on a phase difference between a first signal and a second signal; and a reference circuit operatively connected to the charge pump and arranged to adjust the charge pump so that the charge pump operates substantially independent of an aging effect.
According to one aspect of the present invention, a method comprises detecting a phase difference between a first signal and a second signal; generating a current dependent on the detecting; and adjusting the current dependent on a reference circuit that is responsive to an aging effect.
According to one aspect of the present invention, an apparatus comprises means for detecting a phase difference between a first signal and a second signal;

Affiliated with

Also associated with

Rating

Variation reduction technique for charge pump transistor aging does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Variation reduction technique for charge pump transistor aging, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Variation reduction technique for charge pump transistor aging will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3278441