Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device
Patent
1996-01-25
1998-06-02
Thomas, Tom
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
Having specific type of active device
257202, 257203, 257204, H01L 2710
Patent
active
057604282
ABSTRACT:
A gate array masterslice having a minimal input/output slot and variable pad pitch architecture is disclosed. In the masterslice, many identical input/output slots ring the periphery of a semiconductor substrate and contain only the special devices necessary for input/output circuits. Each of the input/output slots include (i) a first region containing a plurality of tuning transistors of different sizes, (ii) a second region having one or more PMOS transistors, each of a size greater than any one of the plurality of tuning transistors, (iii) a third region having one or more NMOS transistors, each of a size greater than any one of the plurality of tuning transistors, and (iv) a fourth region containing one or more devices for providing electrostatic discharge protection. One to four PMOS transistors are provided in the second slot region and one to four NMOS transistors are provided in the third slot region. A plurality of bonding pads are provided, at least some of which are electrically connected to at least some of the input/output slots such that the plurality of bonding pads may have a variable bonding pad pitch.
REFERENCES:
patent: 3968478 (1976-07-01), Mensch, Jr.
patent: 4431928 (1984-02-01), Skokan
patent: 4600995 (1986-07-01), Kinoshita
patent: 4668972 (1987-05-01), Sato et al.
patent: 4766475 (1988-08-01), Kawashima
patent: 4864381 (1989-09-01), Seefeldt et al.
patent: 4893168 (1990-01-01), Takahashi et al.
patent: 4910680 (1990-03-01), Hiwatashi
patent: 4920398 (1990-04-01), Yoshio et al.
patent: 4945395 (1990-07-01), Suehiro
patent: 4947233 (1990-08-01), Aso
patent: 4975758 (1990-12-01), Crafts
patent: 4978633 (1990-12-01), Seefeldt et al.
patent: 4987578 (1991-01-01), Akins et al.
patent: 4988636 (1991-01-01), Masleid et al.
patent: 4992845 (1991-02-01), Arakawa et al.
patent: 5019889 (1991-05-01), Yoshio et al.
patent: 5045913 (1991-09-01), Masleid et al.
patent: 5063429 (1991-11-01), Crafts
patent: 5087955 (1992-02-01), Futami
patent: 5162893 (1992-11-01), Okano
patent: 5291043 (1994-03-01), Arakawa
patent: 5300796 (1994-04-01), Shintani
patent: 5347150 (1994-09-01), Sakai et al.
patent: 5365091 (1994-11-01), Yamagishi
patent: 5422441 (1995-06-01), Iruka
patent: 5581202 (1996-12-01), Yano et al.
patent: 5610417 (1997-03-01), Doi
patent: 5698873 (1997-12-01), Colwell et al.
SGS-Thomson Microelectronics, "ISB35000 Series, HCMOS Structured Array," (Jan. 1994).
Sub-Micron Chip ESD Protection Schemes Which Avoid Avalanching Junctions, by E.R. Worley et al., EOS/ESD Symposium (1995).
Novel Clamp Circuits for IC Power Supply Protection, by Timothy J. Maloney, et al., EOS/ESD Symposium (1995).
Colwell Michael J.
Roddy Stephen P.
Hardy David B.
LSI Logic Corporation
Thomas Tom
LandOfFree
Variable width low profile gate array input/output architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Variable width low profile gate array input/output architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Variable width low profile gate array input/output architecture will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1462782