Multiplex communications – Communication over free space – Combining or distributing information via frequency channels
Reexamination Certificate
2000-03-02
2004-03-30
Nguyen, Chau (Department: 2663)
Multiplex communications
Communication over free space
Combining or distributing information via frequency channels
C370S481000, C370S485000
Reexamination Certificate
active
06714529
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital demultiplexer, a digital multiplexer, and a digital modem used in radio communication and the like, and relates in particular to a digital modem whose transmission speed can be varied readily.
This application is based on patent applications Nos. Hei 11-056772 and Hei 11-222053 filed in Japan, the contents of which are incorporated herein by reference.
2. Description of the Related Art
First, conventional digital multiplexer and demultiplexer will be explained.
When a device for multiplexing or demultiplexing a number of frequency-multiplexed channels is made using analogue circuits, it is necessary to employ as many local oscillators and band-stop filters as there are channels such that the scale of the device and power consumption are inevitably increased. In the meanwhile, with the widespread use of digital signal processing technologies, digital multi/demultiplexers have been made possible, resulting in miniaturization and low power consumption of such devices.
In particular, digital multi/demultiplexers based on multi-rate signal processing theory is an effective construction method for such devices because of the high degree of freedom in providing channel separation and selecting bandwidths.
FIG. 20
shows an example of the structure of a 4-digital signal demultiplexer for demultiplexing frequency-multiplexed signals, such as those shown in FIG.
22
. This structure is the same as one reported in a reference, K. Yamano, “Fast Frequency Search and Demodulation with Complex Multi-Rate Filter Banks”, ITE Technical Report, ROFT96-46.
The device shown in
FIG. 20
is comprised by: an orthogonal detector
201
; A/D converters
202
,
203
; 2-demultiplexing filter banks
204
,
205
,
206
; high pass filters
2041
,
2051
,
2061
; low pass filters
2042
,
2052
,
2062
; down-samplers
2043
,
2044
,
2053
,
2054
,
2063
,
2064
; and wave shaping filters
2072
,
2073
,
2074
.
The properties of each high pass filter
2041
,
2051
,
2061
are the same when standardized by the sampling frequency, and can be expressed as in the part (a) in FIG.
30
. In this graph, fs relates to a sampling speed at the input of split filters. Similarly, the properties of low pass filters
2042
,
2052
,
2062
can be shown by the part (b) in FIG.
30
.
Received signals are input in the orthogonal detector
201
, and are converted to in-phase components and orthogonal components. Analogue signals of in-phase and orthogonal components output from the orthogonal detector
201
are respectively converted to digital signals in the A/D converters
202
,
203
, and are input in the split filter bank
204
. The signals are separated into two groups in the split filter bank
204
, and are respectively input in the high pass bank
2041
and the low pass filter
2042
for limiting the bandwidths.
Bandwidth-limited signals are input into respective down-samplers
2043
,
2044
and are culled to 1/2 by down-sampling. Signals output from the down-sampler are input in the serially-connected split filter banks
205
,
206
. Signals are split into two groups in the split filter banks
205
,
206
are input into high pass filters
2051
,
2061
and low pass filters
2052
,
2062
, respectively.
Bandwidth-limited signals are respectively input in the down-samplers
2053
,
2054
,
2063
,
2064
, and are down-sampled to 1/2 at the timing shown in
FIG. 6
, and are wave shaped in
2071
,
2072
,
2073
,
2074
, and are output as four independent signal groups shown in FIG.
22
.
Signal spectra at the points A, B, C, D of the signal processed through the components
2041
,
2043
,
2051
,
2053
indicated in
FIG. 20
are shown, respectively, in the parts (a)~(e) in FIGS.
23
~
24
. Circled numbers refer to separate source signals and are used throughout in the same manner in the following presentation.
Next, an example of the structure of 4-wave digital multiplexer with input of four separate signal groups is shown in FIG.
21
. The vectors for each signal are shown in FIG.
25
. The device is comprised by: 2-multiplexing filter banks
212
,
213
; up-samplers
2111
,
2112
,
2121
,
2122
,
2131
,
2132
; high pass filters
2113
,
2123
,
2133
; low pass filters
2114
,
2124
,
2134
; low pass filters
2114
,
2124
,
2134
; adders
2115
,
2125
,
2135
; A/D converters
214
,
215
; orthogonal modulator
216
; and wave shaping filters
2171
,
2172
,
2173
,
2174
.
Four groups of different baseband signals are input in filters
2171
,
2172
,
2173
,
2174
in two separate groups. The output from the wave shaping filters are input in the 2-multiplexing filter banks
211
,
212
, and are up-sampled in the up-samplers
2111
,
2112
,
2121
,
2122
to double the sampling speed at the timing shown in FIG.
12
.
Signals output from the up-samplers
2111
,
2112
are input in the high pass filter
2113
and the low pass filter
2114
, respectively, and are added in the adder
2115
. Similarly, signals output from the up-samplers
2121
,
2122
are input in the high pass filter
2123
and the low pass filter
2124
, respectively, and are added in the adder
2125
. Signals output from the 2-multiplexing filter banks
211
,
212
are input in the 2-multiplexing filter bank
213
.
Input signals are input in the up-sampler
2131
,
2132
that interpolates to twice the size at the timing shown in FIG.
12
. Signals output from the up-samplers
2131
,
2132
are input in the highpass filter
2133
and the low pass filter
2134
, respectively, and are added in the adder
2135
. Signals output from the 2-multiplexing filter bank
213
is input in the D/A converters
214
,
215
and are then converted to desired radio frequencies in the orthogonal converter
216
.
Signal spectra at the points A, B, C, D, E, F, G of the signals processed through the components
2111
,
2113
,
2115
,
2131
,
2133
,
2135
indicated in
FIG. 21
are shown, respectively, in the parts (a)~(g) in FIGS.
26
~
28
.
Next, conventional digital modem and its operation will be explained.
FIG. 40
shows a construction of a conventional digital modem, and shows the transmitter side of the device for providing different transmission speeds based on a frequency division multiple access (FDMA) system.
The device is comprised by: serial-parallel conversion circuit
7001
; modulation circuits
7002
~
7009
; low pass filters
7010
~
7017
; local oscillator circuits
7018
~
7025
; sending circuit
7026
; control circuit
7027
; and frequency conversion circuits
7028
~
7035
.
In the configuration shown in
FIG. 40
, maximum number of carrier frequencies is eight. In the device shown in
FIG. 40
, input digital signals are input in the serial-parallel conversion circuit
7001
and are converted to a maximum of eight parallel data under the control of the control circuit
7027
according to the signal inputting speed.
The parallel data are all transmitted at the same speed represented by Fb. Output signals from the serial-parallel conversion circuit
7001
are input into a maximum of eight groups in the eight modulation circuits, and are output as a maximum of eight groups of complex modulated signals.
Complex modulated signals output from the modulation circuits
7002
~
7009
are input in the low pass filters
7010
~
7017
to limit the bandwidth, and are converted to respective signals of different frequencies by the local oscillators
7018
~
7025
, are multiplexed by the multiplexer
7036
, and are input in the sending circuit to be transmitted from the antennae.
FIG. 41
shows an example of the structure of the conventional digital signal receiver, and shows the receiver side of the device for providing different transmission speeds based on a frequency division multiple access (FDMA) system. The device is comprised by: receive circuit
7101
; local oscillators
7102
~
7109
; low pass filters
7110
~
7117
; demodulation circuit
7118
~
7125
; parallel-serial conversion circuit
7126
; control circuit
7127
; and frequency conversion circuits
7128
~
7135
.
Sig
Kazama Hiroshi
Kobayashi Kiyoshi
Tanabe Kazuhiro
Juntima Nittaya
Krebs Robert E.
Nguyen Chau
Nippon Telegraph and Telephone Corp.
Thelen Reid & Priest LLP
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