Variable timing circuit for card readers and the like

Details Variable timing circuit for card readers and the like Variable timing circuit for card readers and the like

1977-07-25

1979-06-19

Kilgore, Robert M.

Registers

Coded record sensors

Particular sensor structure

3401463AG, 360 42, 360 62, G06K 710, G06K 900, G11B 509, G11B 1512

Patent

active

041584368

ABSTRACT:
A circuit is disclosed for use in magnetic card readers to compensate for variations in card speed as a card moves under a read head. The subject circuit decodes two frequency coherent phase encoding. This self clocking binary code incorporates the presence or absence of pulses (or transitions of voltage levels) within periodic intervals or bit cells as a representation of a logic 1 or a logic 0 respectively.

REFERENCES:
patent: 3599151 (1971-08-01), Harr
patent: 3727202 (1973-04-01), Fort
patent: 3748442 (1973-07-01), Lovendusky
patent: 3784792 (1974-01-01), Dobras
patent: 3784795 (1974-01-01), Tuhro
patent: 3836753 (1974-09-01), Pass
patent: 3893170 (1975-07-01), Kellner
patent: 3896293 (1975-07-01), Pass
patent: 3909594 (1975-09-01), Allais
patent: 3930266 (1975-12-01), Okamoto
F. C. Marino, "Digital Data: Play It Like It Is", The Electronic Engineer, pp. 74-78, Jun. 1969.

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