Active solid-state devices (e.g. – transistors – solid-state diode – With specified dopant
Reexamination Certificate
1999-03-04
2001-04-24
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
With specified dopant
C257S345000, C257S385000
Reexamination Certificate
active
06222251
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention pertains in general to silicon gate CMOS technology and, more particularly, to the fabrication of the silicon gate electrode and the doping profile across the gate electrode from the upper surface to the gate oxide boundary.
BACKGROUND OF THE INVENTION
With the advent of polycrystalline silicon technology, the MOS transistor comprised of a layer of polysilicon disposed over a channel region and separated therefrom by a gate oxide has been a mainstay for the fabrication process of MOS transistors. In the early days of this technology, a conformal layer of polysilicon was first disposed over the substrate and then patterned to form the gate electrodes of the MOS transistors within the various active regions. Thereafter, this gate electrode was utilized as the mask to define the channel regions, wherein an implant step was operable to form source/drain regions on either side of the channel. This was acceptable for early integrated circuits, as the size of the transistors was quite large. However, as device sizes have been scaled down with the advent of new technology, the gate electrodes have become much narrower and thinner, this in and of itself presenting some difficulties and challenges to the designer.
The quality of a transistor is affected by the doping level in the polysilicon. Typically, the conductivity of the polysilicon is increased as much as possible and, therefore, it is heavily doped. In early CMOS devices, the polysilicon that was utilized to form the gate electrode was typically subjected- to a uniform doping of one impurity type, such as N-type impurities. For N-channel transistors, this resulted in the formation of an acceptable transistor. This was due to the fact that the majority carrier in the gate was opposite to the majority carrier in the channel region. In the P-channel device, the opposite condition was present. Typically, a threshold adjust implant was required in the P-channel transistor. As transistor technology advanced, the gate electrodes for P-channel transistors were doped separately from those for N-channel transistors, such that P-type impurities were introduced into the gate electrodes associated with P-channel transistors.
Typically, the doping level in the gate electrode is relatively high. This is for the purpose of minimizing the voltage dependency of the gate oxide thickness. For low doping levels in the gate electrode, a high voltage associated with a transistor that is turned on will result in a depletion region forming in the gate electrode adjacent to the gate oxide boundary. This will increase the effective gate oxide thickness. This can be detrimental to frequency response and other parameters of the transistor. By increasing the doping level, this depletion region is minimized, as majority carriers adjacent to the gate/oxide boundary are depleted. Of course, in some situations, such as that for high voltage transistors, it is desirable to have the gate oxide thickness increase with voltage. This, of course, is not true for small signal transistors.
SUMMARY OF THE INVENTION
The present invention disclosed and claimed herein comprises a method for forming a gate electrode for an MOS transistor. The MOS transistor is formed in a substrate of a first conductivity type with a gate electrode provided overlying the channel region of the transistor and separated therefrom by a layer of gate oxide. The gate electrode is formed such that it has a graded doping profile with a concentration of first conductivity type dopants therein that have a relatively high concentration at the upper surface thereof, which concentration decreases from the upper surface of the gate electrode to a point proximate to the gate oxide layer.
In another aspect of the present invention, the graded doping profile of the first conductivity type dopants decreases from a relatively high concentration at the upper surface of the gate electrode to a lower concentration at a point proximate to but spaced away from the gate oxide layer. This allows a region of conductive material disposed proximate to the gate oxide layer that has a minimal concentration of first conductivity type dopants therein. The region with minimal first conductivity dopants therein is lightly doped with second conductivity type dopants.
In a further aspect of the present invention, the gate electrode is formed by first forming a layer of polysilicon over the gate oxide layer in the transistor active region, which first layer of polysilicon is doped with second conductivity type dopants in a light concentration during the deposition of the first layer. Thereafter, a second layer of polysilicon is deposited onto the substrate having a light concentration of first conductivity type dopants therein. This concentration of dopants in the second layer of polysilicon is higher than the concentration of the dopants of the second type conductivity in the first layer.
REFERENCES:
patent: 4990974 (1991-02-01), Vinal
patent: 5371396 (1994-12-01), Vinal et al.
patent: 5514902 (1996-05-01), Kawasaki et al.
Brady III Wade James
Garner Jacqueline J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Thomas Tom
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