Variable signal delaying circuit, quadrature frequency...

Pulse or digital communications – Receivers – Angle modulation

Reexamination Certificate

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Details

C455S260000, C455S323000, C455S180300

Reexamination Certificate

active

07606332

ABSTRACT:
A variable signal delaying circuit comprising an analog delay line having a control input for controlling the variable delay. A phase detector compares the input and output signals of the delaying circuit and supplies an output signal to a charge pump and integrator. A pulse stream generating arrangement produces pulse streams of different pulse widths and pulse control logic controls a selector for selecting any one of the pulse streams. In a first mode of operation, the control logic monitors the charge pump/filter output and selects the pulse stream which minimizes change in the output. The selection is fixed and the output of the charge pump/filter is then supplied as a correction signal to the control input of the analog delay line. Such an arrangement may be used to maintain minimum phase imbalance in I and Q signal paths of a quadrature frequency converter.

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patent: 4025245 (1992-01-01), None
patent: 6097755 (1994-04-01), None

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