Variable rotational assignment of interconnect levels in...

Details Variable rotational assignment of interconnect levels in... Variable rotational assignment of interconnect levels in...

2005-02-01

2005-02-01

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S296000, C438S130000, C438S128000, C382S296000, C382S298000, C382S300000

Reexamination Certificate

active

06849937

ABSTRACT:
Integrated circuit fabrication techniques are provided which allow non-horizontal
on-vertical wires to traverse the entire chip surface, rather than just the corners as in the conventional Manhattan geometry, while interconnecting circuit points. This is achieved by employing a variable rotational assignment methodology with respect to the interconnect layers or levels during the IC fabrication operation. These techniques thus eliminate the litho step problem, reduce interconnect distances and lessen the influence of capacitance interaction between interconnect wires.

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