Variable resistor circuit and a digital-to-analog converter

Details Variable resistor circuit and a digital-to-analog converter Variable resistor circuit and a digital-to-analog converter

2000-09-06

2001-03-20

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S143000, C338S334000

Reexamination Certificate

active

06204789

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-251923, filed Sep. 6, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a variable resistor circuit and a digital-to-analog converter in which the variable resistor circuit is employed as a feedback resistor. More specifically, the present invention relates to a variable resistor circuit of digital control which is controlled by an output signal of a counter and a zero detect mute circuit of an output circuit section in a digital-to-analog converter in which a sigma-delta modulator is employed.
Conventionally, an output circuit section of a digital-to-analog converter (D/A converter) in which a sigma-delta modulator is employed is constituted, for example, as shown in
FIG. 1. A
multibit digital signal is inputted to a sigma-delta modulator
11
. One bit output signal NRZ of this sigma-delta modulator
11
is supplied to one side input terminal of an AND gate
12
and is inverted so as to be supplied to one side input terminal of a NAND gate
13
. A clock signal CK is supplied to the other input terminal of the AND gate
12
, and the clock signal CK is supplied to the other input terminal of the NAND gate
13
.
An output signal RZ of the AND gate
12
is supplied to one end of a resistor
15
via an inverter
14
, and an output signal RZn of the NAND gate
13
is supplied to one end of a resistor
17
via an inverter
16
. The other ends of the resistors
15
,
17
are connected to one end of a resistor
18
, and the other end of the resistor
18
is connected to one end of a resistor
19
. A capacitor
20
is connected between the one end of the resistor
18
and ground point GND, and a capacitor
21
is connected between the other end of the resistor
18
and ground point GND. The other end of the resistor
19
is connected to the inverting input terminal (−) of an operational amplifier (op-amp)
22
, and the non-inverting input terminal (+) of this op-amp
22
is connected to ground point GND.
A capacitor
23
and a resistor
24
are connected in parallel between the output terminal and the inverting input terminal (−) of the op-amp
22
so that an output signal PRZ is feedback to the inverting input terminal (−).
The 1-bit output signal NRZ outputted from the sigma-delta modulator
11
typically becomes that as shown in a timing chart of FIG.
2
. The output signal RZ of the AND gate
12
is an AND (logical product) of the 1-bit output signal NRZ and the clock signal CK, and the output signal RZn of the NAND gate
13
is a NAND (NOT-AND) of the inverted signal of the 1-bit output signal NRZ and the clock signal CK. The output signal PRZ of the D/A converter has a waveform made by synthesizing the output signal RZ of the AND gate
12
and the output signal RZn of the NAND gate
13
.
In the D/A converter, there are many cases in which a function (hereafter, zero detect mute function) is required in which it is detected that an input digital signal is zero data for a constant period of time and the output is fixed to a constant DC value (typically, mid electric potential). That is, generally, there are many cases in which a large scale of digital circuit exists on the same chip or the same board in a D/A converter, and a large amount of unnecessary radiation bursts in on the D/A converter from the digital circuit via space or a power supply line as a noise. In the sigma-delta modulator
11
, even when the zero data are inputted, the 1-bit output signal does not become the DC value but becomes a waveform containing an extremely high frequency noise due to a requantization noise. Thus, even though nothing is essentially supposed to be outputted when an inputted digital signal is zero data, there are many cases in which an unpleasant sound is emitted and/or a poor value is outputted at measurement of a signal-to-noise ratio due to the noise.
In order to prevent this from occurring, when zero data continue for a constant period of time (typically, approximately 100 msec), a zero detect mute function in which said condition is detected and an analog signal of the D/A converter is fixed to a ground potential or reference potential is employed. Since the reference potential is typically decoupled by a capacitor with a large amount of capacitance, mixing of noise is small, thereby preventing an unpleasant sound from being emitted and/or a measured value of an S/N ratio from becoming poor by the mute function.
FIG. 3
shows a structural example of an output circuit section of a conventional D/A converter with the zero detect mute function described above. This output circuit section performs on/off control for an output signal MUTE of a zero detect circuit
26
by connecting an analog switch circuit
25
between the output terminal and the inverting input terminal (−) of the op-amp
22
in the circuit shown in
FIG. 1
mentioned above. A multibit digital signal is inputted to the zero detect circuit
26
, and in this zero detect circuit
26
, it is decided whether or not the feedback resistor
24
of the op-amp
22
is short-circuited, in other words, mute on/off is decided.
In this type of circuit structure, when it is detected that zero data continues for a constant period of time as a multibit digital signal by means of the zero detect mute circuit
26
, by turning the analog switch circuit
25
on, the feedback resistor (resistor
24
) of the op-amp
22
is short-circuited, thereby preventing an unpleasant sound from being emitted and/or a measured value of an S/N ratio from becoming poor by noise.
However, in the circuit structure described above, there is a big problem in performing the on/off of the mute by the zero detection. That is, click sounds occur at the time of mute on/off. Although this click sound occurs since the DC values at the times of mute ON and mute OFF are different, the causes are various as described below.
First, there is a click sound due to a digital DC offset. Typically, in the D/A converter with the zero detect mute function, in order to prevent the problem that is peculiar to the sigma-delta modulator wherein a fixed pattern occurs at the time of inputting the zero data, thereby causing a unpleasant beat sound, there are many cases in which an adder
27
is provided in the input terminal of the sigma-delta modulator
11
as shown in
FIG. 4
so that a digital DC offset as shown in
FIG. 5
is added to the input signal of the sigma-delta modulator
11
in advance. With this, as a matter of course, an analog DC offset corresponding to the input digital DC offset is outputted, and thus the click sound occurs at the time of mute on/off.
Therefore, a method is adopted in which an adder
28
is provided between the other ends of the resistors
15
,
17
and the one end of the resistor
18
so that an analog DC offset for canceling the digital DC offset is added. However, the DC offset cannot be cancelled completely under the influence of element accuracy or element unevenness or the like, whereby a little DC offset remains.
Second, there is a DC offset due to waveform blunting or element unevenness of the D/A converter (hereafter DAC), in other words, there is a DC error as a DAC.
Lastly, there is an equivalent input DC offset of the op-amp
22
. As shown in
FIG. 6
, when the feedback resistor
24
is short-circuited by the analog switch circuit
25
so as to perform the mute, in the op-amp
22
having the equivalent input DC offset, that is, EOS, this EOS's DC displacement (2EOS at the time of mute off, EOS at the time of mute ON) occurs at the mute on/off so as to become a click sound.
Although the causes described above may be made reduced by a device in a circuit structure, an improvement in element accuracy, a restraint in element unevenness, or the like, they cannot be eliminated completely. That is, a little DC displacement inevitably occurs at the mute on/off, and a click sound

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