Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2007-04-03
2010-10-19
Hur, J. H. (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S163000, C365S051000, C365S072000
Reexamination Certificate
active
07817454
ABSTRACT:
A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations.
REFERENCES:
patent: 6687147 (2004-02-01), Fricke et al.
patent: 6862214 (2005-03-01), Lee et al.
patent: 6894916 (2005-05-01), Reohr et al.
patent: 2003/0012064 (2003-01-01), Beretta
patent: 2004/0170053 (2004-09-01), Lee et al.
patent: 2006/0176724 (2006-08-01), Asano et al.
patent: 2006/0209585 (2006-09-01), Tanizaki et al.
patent: 2007/0120128 (2007-05-01), Sato et al.
patent: 2007/0171706 (2007-07-01), Fuji
patent: 10-0681810 (2007-02-01), None
Lacaita, A.L., “Phase Change Memories: State-of-the-art, Challenges and Perspectives”, Solid-State Electronics, Oct. 10, 2005, pp. 24-31.
Hudgens, S. et al., “Overview of Phase-Change Chalcogenide Nonvolatile Memory Technology”, MRS Bulletin, Nov. 2004, pp. 829-832.
Lee, S.H. et al., “Full Integration and Cell Characteristics for 64Mb Nonvolatile PRAM”, 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 20-21.
Lai, Stefan, “Current Status of the Phase Change Memory and its Future”, Intel Corporation, Santa Clara, CA.
Wuttig, Matthias, “Towards a Universal Memory?”, Nature Materials, Apr. 2005, pp. 265-266, vol. 4, Nature Publishing Group.
Dickstein & Shapiro LLP
Hur J. H.
Micro)n Technology, Inc.
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