Variable refresh intervals for system devices including setting

Details Variable refresh intervals for system devices including setting Variable refresh intervals for system devices including setting

1995-02-17

1997-06-10

Chan, Eddie P.

G06F 1216

Patent

active

056385293

ABSTRACT:
An apparatus is provided for controlling a memory refresh operation in a computer system having a processor coupled to a host volatile memory via a memory controller, a system bus controller coupled to the processor via the memory controller, and a plurality of devices coupled to the system bus controller via a system bus. The apparatus includes a first timer coupled to the memory controller for generating a first memory refresh signal at a first predetermined time interval to cause the memory controller to perform the memory refresh operation on the host volatile memory. A second timer is coupled to the system bus controller for generating a second memory refresh signal at a selective time interval to causes the system bus controller to perform the memory refresh operation on the plurality of devices. A program is provided for detecting the refresh requirement of the plurality of devices in order to determine the selective time interval. When the program detects that one of the plurality of devices requires the memory refresh operation, the program sets the selective time interval to a second predetermined time interval. When the program detects that none of the plurality of devices requires the memory refresh operation, the program switches off the second timer. A method of controlling the memory refresh operation is also described.

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