Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal
Reexamination Certificate
1998-10-09
2001-07-17
Kelley, Chris (Department: 2713)
Pulse or digital communications
Bandwidth reduction or expansion
Television or motion video signal
Reexamination Certificate
active
06263019
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to decoders for processing image data which has been compressed according to a format, MPEG-
2
, specified by the moving pictures experts group (MPEG) and in particular to a decoder in which different time intervals may be assigned to the decoding of respective segments of the MPEG-
2
bit-stream.
Video signal compression performed under the MPEG-
2
standard is inherently variable rate. Video data is compressed based on the spatial frequency content of either a sequence of images or on differences in spatial frequency content among the individual images in the sequence.
The syntax for the MPEG-
2
standard is set forth in International Standard 13818-2 Recommendation ITU-T H.262 entitled “Generic Coding of Moving Pictures and Associated Audio Information: Video” and available from ISO/IEC, Geneva, Switzerland, which is incorporated herein by reference for its teaching of the MPEG-
2
video coding standard. This standard defines several layers of data records which are used to convey both audio and video data. For the sake of simplicity, the decoding of the audio data is not described herein. Encoded data which describes a particular video sequence is represented in several nested layers, the Sequence layer, the Group of Pictures layer, the Picture layer, the Slice layer and the Macroblock layer. Each layer record except for the Macroblock record begins with a start code that identifies the layer. The record includes header data and payload data.
The Sequence layer defines parameters such as picture size and aspect ratio which affect the decoding of a relatively large number of successive images. The Group of Pictures layer defines parameters for a smaller number of images and the Picture layer defines parameters for a single image. Inside of an image, a Slice record defines parameters for a horizontal segment of the image which is composed of multiple Macroblocks.
Thus, the actual image data is in the Macroblock layer. In a typical MPEG-
2
bit-stream, there are many more Macroblock and Slice records than Picture, Group of Picture and Sequence records. Accordingly, the headers for the Sequence records, Group of Picture records and Picture records may be decoded using algorithms implemented in software which run on a conventional microprocessor. Slice records and Macroblock records, however, occur more frequently in the bit-stream and are typically decoded using special purpose hardware.
In a typical decoder, the circuitry used to decode the headers of the Slice and Macroblock records is constrained by the circuitry used to decode the payload of the Macroblock records. If any change is made in the Macroblock decoding process, a corresponding change is typically made to the circuitry which processes the Slice and Macroblock headers. If, for example, an existing Macroblock decoder is implemented using a semiconductor process technology having a smaller geometry (e.g. translated from a one micron process to a half-micron process), it may be necessary to redesign the hardware that decodes the Slice and Macroblock headers so that the complete bit-stream is processed properly.
SUMMARY OF THE INVENTION
The present invention is embodied in apparatus for decoding a digitally encoded signal. The apparatus includes a state machine which parses header information in the encoded signal. The state machine defines states corresponding to discrete parsing operations. Each state in the state machine includes a defined processing time for the state. A transition from one state to the next is not implemented until the end of the defined time regardless of whether the actual processing operations performed by the state are complete. The processing time for each state is set by a microprocessor coupled to the state machine. These processing times may be changed based on image content or to accommodate changes in the circuitry used to implement the state machine. The processing times for the state changes may also be adjusted to accommodate changes in other processing elements which are coupled to the state machine.
According to one aspect of the invention, the state machine decodes MPEG-
2
encoded image data, parsing the MPEG-
2
syntax for the Slice and Macroblock layers.
According to yet another aspect of the invention, a predetermined number of decoding cycles are defined for decoding the image and the microprocessor adjusts the assigned processing times to fit the total processing time for the image into the predetermined number of decoding cycles.
REFERENCES:
patent: 4468688 (1984-08-01), Gabriel et al.
patent: 4472732 (1984-09-01), Bennett et al.
patent: 4908874 (1990-03-01), Gabriel
patent: 5327235 (1994-07-01), Richards
patent: 5489903 (1996-02-01), Wilson et al.
patent: 5623311 (1997-04-01), Phillips et al.
patent: 5737019 (1998-04-01), Kim
patent: 5812760 (1998-09-01), Mendenhall et al.
patent: 5812791 (1998-09-01), Wasserman et al.
patent: 5940016 (1999-08-01), Lee
patent: 6018776 (2000-01-01), Wise et al.
Winzker et al. “Architecture and Memory Requirements for stand-alone and hierarchical MPEG2 HDTV-Decoders with Synchronous DRAMs”IEEEApr. 30, 1995 pp. 609-612.
Jill Boyce et al. SDTV REceivers with HDTV Decoding Capability Feb. 1995, ACATS Technical Subgroup Meeting, May 1995, Washington DC.
K. Blair Benson et al. Television Engineering Handbook featuring HDTV Systems (Revised Edition), pp. 18.2 to 18.7 1986 McGraw/Hill 18.
Jill Boyce et al. Low-Cost All Format ATV Decoding with Improved Quality, Hitachi America, Ltd, Princeton, N.J., 30th SMPT Advanced Motion Imaging Conference, Paper #11, Feb. 2, 1996.
Jack S. Fuhrer, The All Format Decoder, Hitachi America, Ltd. Jun. 3, 1996.
Recommended Practices for Video Encoding Using the ATSC Digital Televion Standard—Consideraton of Downsampling Decoders,SMPTE Jun. 6, 1996. Discussion on Recommended Practices for North American ATV Video Coding—Consideration of Downsampling Decoders, Hitachi May 1996.
Discussion on Recommended Practices for North American ATV Video Coding—Consideration of Downsampling Decoders, Hitachi May 1996.
M. Stojancic et al. Architecture & VLSI Implementation of the MPEG-2 MP@ML Video Decoding Process 8012SMPTE Journal104, Feb. 1995, No. 2.
Kelley Chris
Matsushita Electric - Industrial Co., Ltd.
Philippe Gims
Ratner & Prestia
LandOfFree
Variable rate MPEG-2 video syntax processor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Variable rate MPEG-2 video syntax processor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Variable rate MPEG-2 video syntax processor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2488553