Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
1999-08-26
2001-03-20
Banks, Derris H. (Department: 3723)
Abrading
Abrading process
Glass or stone abrading
C451S286000
Reexamination Certificate
active
06203408
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Technical Field
This invention relates to a method which varies the amount of pressure applied to specific areas of a semiconductor during polishing and permits more accurate control of the polishing rate across the semiconductor surface when performing chemical mechanical polishing (CMP) to produce a uniform substrate surface.
(2) Description of the Prior Art
The following documents relate to a method for controlling a polishing rate across a substrate surface when performing CMP.
U.S. Pat. No. 5,423,716 issued Jan. 5, 1994 to Alan Strasbaugh describes an apparatus for holding a wafer which includes a soft, resilient membrane that covers a horizontal backing plate. The lower face of the backing plate includes a number of recessed areas to which vacuum can be selectively applied. By applying a pressurized fluid to the recessed areas during polishing, the membrane will exert a uniform downward pressure on the wafer and produce a uniformly polished surface.
U.S. Pat. No. 5,624,299 issued May 1, 1995 to Norman Shendon describes a carrier apparatus for positioning and biasing a substrate against a polishing pad. The device uses a membrane configured to create one or more vacuum regions which chuck the substrate to the membrane so that the carrier may move the substrate on and off the polishing pad.
U.S. Pat. No. 5,800,248 issued Apr. 26, 1996 to Anil K. Pant et al describes a support housing which underlies a polishing pad and includes a plurality of openings for dispensing a pressurized fluid.
The manufacture of an integrated circuit device requires the formation of various layers (both conductive and non-conductive) above a substrate to form the necessary components and interconnects. During the manufacturing process, certain layers or portions of layers must be removed in order to pattern and form the various components and interconnects. Chemical mechanical polishing (CMP) is the method of choice for planarization of a surface of a semiconductor wafer, such as a silicon wafer, at various stages of the integrated circuit processing. CMP is also used to flatten optical surfaces, metrology samples and in various metal and semiconductor based substrates.
CMP is a technique in which a chemical slurry is used in conjunction with a mechanical polishing pad to polish away materials on a semiconductor wafer. The mechanical movement of the pad relative to the wafer (and in conjunction with the slurry) provides the abrasive force to polish the exposed surface of the wafer. In the most common form of CMP, a substrate is mounted on a polishing head which rotates against a polishing pad placed on a rotating table. The mechanical force derives from the rotating table speed and the downward pressure on the head. The chemical slurry is constantly transferred under the polishing head. Rotation of the polishing head helps in the slurry delivery as well as in averaging the polishing rates across the substrate surface. A constant problem of CMP is that the polishing rate varies from the periphery to the center of the wafer for various reasons. Pad bounce is one reason. Variations in the velocity encountered in the rotational movement is another. Some amount of averaging is achieved by rotating the wafer but variations still result in non-uniform polishing across the wafer surface. It is an important goal in the CMP processing to try to minimize this inequality in polishing rates.
One approach utilizes a linear polisher as opposed to a rotating one. A moving belt linearly moves the pad across the wafer surface. The wafer is still rotated for averaging out the local variations, but the global planarity is improved over CMP tools using rotating pad.
SUMMARY OF THE INVENTION
Currently all carrier types have holes in the base to allow vacuum pressure to hold the wafer in place or to push the wafer down using nitrogen or compressed dry air during CMP. The problem has been that all the holes receive the same amount of vacuum or air pressure applied since there is only one regulated source of supply. The result is, with new carrier film and pad, that the wafer tends to polish faster at the center and more slowly at the outer perimeter Over a period of time, the edge will polish faster and the center more slowly.
This invention describes a technique for controlling a polishing rate across a substrate surface in order to obtain a uniform polishing of the substrate surface This invention provides a method for varying the pressure/vacuum to accommodate for changes in the surface of the carrier film over time. The device permits the increase or decrease of pressure applied onto the wafer on any of multiple specific areas and ensures good planarization throughout the life of the consumable (carrier film, polishing pad); it can also prolong the useful life of the consumable.
By having the ability to better control the amount of pressure/vacuum applied to certain areas of the wafer, the invention can fine-tune the polishing procedure and produce a more uniform wafer.
The present invention describes a technique for controlling the polishing rate across a substrate surface during polishing by applying different pressures to a plurality of designated sites of any configuration. A support housing includes a plurality of openings through a shaft for individualized regulated gas pressures. These openings are arranged in a reconfigured pattern to the substrate surface or wafer to be polished. The openings are configured into a number of groupings so that a separate channel with a controlled pressure is used for each grouping. It is in this manner that the gas pressure for each grouping can be separately and independently controlled. The individualized regulated pressures may be within the pressure range of between 1.5×10
3
mm Hg to 10
−3
Hg. The ability to control gas pressure at various and specific sites on the wafer permits localized pressure adjustments and ensures that the pad-substrate contact is maintained at the desired levels thereby ensuring a uniform rate of polish along the entire surface of the surface being polished.
REFERENCES:
patent: 3747282 (1973-07-01), Katzke
patent: 5423558 (1995-06-01), Koeth et al.
patent: 5423716 (1995-06-01), Strasbaugh
patent: 5441444 (1995-08-01), Nakajima
patent: 5476414 (1995-12-01), Hirose et al.
patent: 5527209 (1996-06-01), Volodarsky et al.
patent: 5624299 (1997-04-01), Shendon
patent: 5651724 (1997-07-01), Kimura et al.
patent: 5681215 (1997-10-01), Sherwood et al.
patent: 5733182 (1998-03-01), Muramatsu et al.
patent: 5797789 (1998-08-01), Tanaka et al.
patent: 5800248 (1998-09-01), Pant et al.
patent: 5851140 (1998-12-01), Barns et al.
Banks Derris H.
Chartered Semiconductor Manufacturing Ltd.
Ojini Anthony
Pike Rosemary L.S.
Saile George O.
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