Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Nonlinear amplifying circuit
Reexamination Certificate
2002-03-15
2004-06-29
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Nonlinear amplifying circuit
C330S258000, C330S257000
Reexamination Certificate
active
06756841
ABSTRACT:
TECHNICAL FIELD
The invention is related to amplifier circuits having variable offset capability, and applications of such circuits.
BACKGROUND
Amplifier circuits are used to amplify an input electrical signal to provide current or voltage gains or reductions. They may be used to amplify a single ended or a differential signal. In addition, when used in conjunction with an output regenerative latch stage, they can provide a digital output signal (having one of two stable states) that is an indication of a comparison between two single ended input signals or a determination of the magnitude of a differential signal. A basic component of many amplifier circuits is the differential transistor pair used as the input stage of the amplifier.
Most practical implementations of amplifier circuits suffer from manufacturing process-induced variations in the structure of the circuit devices, which cause an offset in the amplifier's operation. The offset may be explained by, for instance, considering an amplifier that is designed to amplify a differential input signal. In some applications, the output of the amplifier would ideally be zero volts if the input differential signal was zero volts. However, in practice, a zero voltage differential signal often yields a small but nevertheless non-negligible output offset voltage. Output offset may be corrected using a wide range of techniques known as offset cancellation techniques. In one such technique, the value of the input differential signal that actually yields a zero output voltage is measured and stored, and then is subsequently subtracted from each new input signal to thus cancel the offset of the amplifier. In other applications of amplifier circuits, such as a pre-amplifier circuit in a comparator circuit, the amplifier circuit is designed to have a specified offset so that a comparison is indicated only when the offset is overcome.
The trend in circuit design is toward smaller and smaller device sizes, which serves not only to minimize space consumption, but also to minimize the capacitance and hence maximize the speed of circuits that incorporate the devices. However, with smaller device sizes, process-induced variations become more of an issue because the probability for process-induced variation in the structure of a device becomes greater as device size becomes smaller.
Amplification of differential signals is often required in the presence of fluctuating common-mode voltages or fluctuating power supply voltages. Because in some cases the signal to be amplified is a differential voltage signal, the amplifier's response to the common-mode voltage or to the power supply voltage produces an error at the output that is indistinguishable from the amplification at the output in response to the input signal. Common mode rejection ratio (CMRR) is conventionally defined as the magnitude of the ratio of differential-mode to common-mode gain, and power supply rejection ratio (PSRR) similarly is conventionally defined as the magnitude of the ratio of differential-mode to power supply gain. Measures of CMRR and PSRR are important benchmarks in circuit performance.
REFERENCES:
patent: 3916333 (1975-10-01), Zuk
patent: 4647839 (1987-03-01), Siligoni et al.
patent: 4754169 (1988-06-01), Morris
patent: 4987327 (1991-01-01), Fernandez et al.
patent: 5043599 (1991-08-01), Zitta
patent: 5079515 (1992-01-01), Tanimoto
patent: 5148162 (1992-09-01), Crosby
patent: 5512848 (1996-04-01), Yaklin
patent: 5517134 (1996-05-01), Yaklin
patent: 5563598 (1996-10-01), Hickling
patent: 5900779 (1999-05-01), Giacomini
patent: 5990737 (1999-11-01), Czarnul et al.
patent: 6018269 (2000-01-01), Viswanathan
patent: 6163215 (2000-12-01), Shibata et al.
patent: 6288588 (2001-09-01), Frisch
patent: 6348882 (2002-02-01), Ciccone et al.
patent: 6388521 (2002-05-01), Henry
patent: 6396329 (2002-05-01), Zerbe
patent: 6420932 (2002-07-01), Casper
patent: 6469576 (2002-10-01), Hasegawa
patent: 6552611 (2003-04-01), Yamamoto
Baker,CMOS Circuit Design, Layout, and Simulation, “Chapter 26: Nonlinear Analog Circuits,” IEEE Press, pp. 685-699.
Ellersick et al., “GAD: A 12-GS/s CMOS 4-bit A/D Converter for an Equalized Multi-Level Link,”1999 Symposium on VLSI Circuits Digest of Technical Papers, pp. 49-52.
Farjad-Rad et al., “A 0.3-&mgr;m CMOS 8-Gb/s 4-PAM Serial Link Transceiver,”IEEE J. Solid State Circuits, 2000, 35(5):757-764.
Yang et al., “A Scalable 32Gb/s Parallel Data Transceiver with On-chip Timing Calibration Circuits,”2000 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 258-259.
Casper Bryan K.
Jaussi James E.
Fish & Richardson P.C. P.A.
Le Dinh T.
LandOfFree
Variable offset amplifier circuits and their applications does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Variable offset amplifier circuits and their applications, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Variable offset amplifier circuits and their applications will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3322352