Variable lock window for a phase locked loop

Details Variable lock window for a phase locked loop Variable lock window for a phase locked loop

2001-05-24

2003-09-02

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331SDIG002, C331S00100A, C327S156000, C375S376000

Reexamination Certificate

active

06614317

ABSTRACT:

BACKGROUND
Processing chips, such as microprocessors, often operate at a relatively high frequency. The frequency may range into the GHz range, and future generations of processors may operate even faster. The processor's operation is stabilized by a stabilized clock source. The clock source may use a phase locked loop (“PLL”).
Processor designs may be relatively complex, and may need debugging during that design phase. It may be difficult to debug a processor at higher frequencies (1 GHz and above) due to lack of high speed measurement systems. Therefore such debugging often starts at lower frequencies and then is debugged at higher frequencies.
Low power processing has also forced the same PLLs to operate at much lower frequencies during battery operated mobile modes versus desktop modes. It may be difficult to allow the same PLL to operate at two extreme frequency corners without losing lock.


REFERENCES:
patent: 5724007 (1998-03-01), Mar
patent: 6211742 (2001-04-01), Tan et al.

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