Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2001-09-18
2003-11-04
Tran, Michael (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185280
Reexamination Certificate
active
06643169
ABSTRACT:
BACKGROUND
This invention relates generally to memory devices and particularly to memory devices with a multi-level cell architecture.
A multi-level cell memory is comprised of multi-level cells, each of which is able to store multiple charge states or levels. Each of the charge states is associated with a memory element bit pattern.
A flash EEPROM memory cell, as well as other types of memory cells, is configurable to store multiple threshold levels (V
t
). In a memory cell capable of storing two bits per cell, for example, four threshold levels (V
t
) are used. Consequently, two bits are designated for each threshold level. In one embodiment, the multi-level cell may store four charge states. Level three maintains a higher charge than level two. Level two maintains a higher charge than level one and level one maintains a higher charge than level zero. A reference voltage may separate the various charge states. For example, a first voltage reference may separate level three from level two, a second voltage reference may separate level two from level one and a third reference voltage may separate level one from level zero.
A multi-level cell memory is able to store more than one bit of data based on the number of charge states. For example, multi-level cell memory that can store four charge states can store two bits of data, a multi-level cell memory that can store eight charge states can store three bits of data, and a multi-level cell memory that can store sixteen charge states can store four bits of data. For each of the N-bit multi-level cell memories, various memory element bit patterns can be associated with each of the different charge states.
The number of charge states storable in a multi-level cell, however, is not limited to powers of two. For example, a multi-level cell memory with three charge states stores 1.5 bits of data. When this multi-level cell is combined with additional decoding logic and coupled to a second similar multi-level cell, three bits of data are provided as the output of the two-cell combination. Various other multi-level cell combinations are possible as well.
The higher the number of bits per cell, the greater the possibility of read errors. Thus, a four bit multi-level cell is more likely to experience read errors than a one bit cell. The potential for read errors is inherent in the small differential voltages used to store adjacent states. If the stored data is potentially lossy, sensitive data stored in relatively high-density multi-level cells may be subject to increased error rates.
In many applications, the nonvolatile memories store a large amount of data that is tolerant to a small number of bit errors. Applications may also have a small amount of data that is not tolerant to bit errors. Examples of such applications may include control structures, header information, to mention a few examples. These typical applications, where a relatively small amount of the overall storage requires higher fidelity, may include digital audio players, digital cameras, digital video recorders, to mention a few examples.
Thus, there is a need for a way to store a large amount of data in dense multi-level cells while ensuring that sensitive data is stored in a fashion that sufficiently reduces the possibility of read errors.
REFERENCES:
patent: 5424978 (1995-06-01), Wada et al.
patent: 5515317 (1996-05-01), Wells et al.
patent: 5812447 (1998-09-01), Inoue
patent: 6097637 (2000-08-01), Bauer et al.
patent: 6097639 (2000-08-01), Choi et al.
patent: 6363008 (2002-03-01), Wong
patent: 0 788 113 (1997-08-01), None
Fackenthal Richard E.
Rudelic John C.
Tran Michael
Trop Pruner & Hu P.C.
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