Variable length shift register alternately operable to store and

Details Variable length shift register alternately operable to store and Variable length shift register alternately operable to store and

1974-08-15

1976-07-27

Fears, Terrell W.

Communications: electrical

Digital comparator systems

340173RC, G11C 1300

Patent

active

039720314

ABSTRACT:
A system for storing and thereafter cyclicly reproducing transient information including nm-element shift registers, either digital or analog, connected in cascade and operable in either (a) a data entry mode for storing transient data therein or (b) a recirculating mode for cyclicly reproducing at the output thereof the information stored therein. A clock of selectively variable frequency is provided for sampling transient information and/or shifting data through the shift register cascade depending upon whether the shift register cascade is in its data storage or its recirculation mode. An addressing circuit responsive to the clock signals for keeping track of the changing address of the stored information currently output from the shift register cascade is provided, and includes a single nm-bit counter in the form of a "divide-by-n" circuit and an "m-counter" circuit connected in series. The output of the m-counter at any given time is correlated to the address of the stored information currently output from the shift register cascade. The address, in combination with the information presented at the output of the shift register cascade, are input to a recording device, such as an oscilloscope, where they control the horizontal and vertical deflection plates to provide a continuous plot with respect to time, of the information recirculating in the shift register cascade. A trigger circuit is provided to reset the divide-by-n and m-counter circuits when it is desired to record new transient information to thereby insure that the addresses of the newly stored transient data will be referenced to the new trigger signal. By altering the divide-by-n circuit such that n always corresponds to the number of m-element registers connected in cascade, proper addresses are provided for information stored and/or recirculating in the shift register cascade regardless of the number of m-element registers actually connected to form the cascade.

REFERENCES:
patent: 3275993 (1966-09-01), Bartlett
patent: 3523284 (1970-08-01), Washizuka
patent: 3763480 (1973-10-01), Weimer
patent: 3772658 (1973-11-01), Sarlo

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