Variable length pipeline processor architecture

Details Variable length pipeline processor architecture Variable length pipeline processor architecture

2005-03-01

2011-12-06

Kindred, Alford (Department: 2181)

Electrical computers and digital processing systems: processing

Instruction issuing

C712S218000

Reexamination Certificate

active

08074056

ABSTRACT:
In one implementation, a pipeline processor is provided having a base architecture that includes one or more decoders operable to decode program instructions and generate one or more decoded instructions, and one or more execution units operable to execute the one or more decoded instructions. Each execution unit includes one or more execution pipeline stages. The pipeline processor architecture further includes one or more additional co-processor pipelines. The one or more decoders of the base architecture are operable to recognize one or more instructions to be processed by a given co-processor pipeline and pass the one or more recognized instructions to the given co-processor pipeline for decoding and execution.

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