Variable-length, high-speed asynchronous decoder circuit

Details Variable-length, high-speed asynchronous decoder circuit Variable-length, high-speed asynchronous decoder circuit

2005-03-08

2005-03-08

Treat, William M. (Department: 2183)

Electrical computers and digital processing systems: processing

Byte-word rearranging, bit-field insertion or extraction,...

C712S208000, C341S065000, C341S067000

Reexamination Certificate

active

06865668

ABSTRACT:
There is disclosed a decoder circuit (20) for decoding input data coded using a variable length coding technique, such as Huffman coding. The decoder circuit (20) comprises an input buffer (100), a logic circuit (150) coupled to the input buffer (100), and an output buffer (700) coupled to the logic circuit (750). The logic circuit (750) includes a plurality of computational logic stages for decoding the input data, the plurality of computational logic stages arranged in one or more computational threads. At least one of the computational threads is arranged as a self-timed ring, wherein each computational logic stage in the ring produces a completion signal indicating either completion or non-completion of the computational logic of the associated computational logic stage. Each completion signal is coupled to a previous computational logic stage in the ring. The previous computational logic stage performs control operations when the completion signal indicates completion and performs evaluation of its inputs when the completion signal indicates non-completion.

REFERENCES:
patent: 5121003 (1992-06-01), Williams
patent: 5784631 (1998-07-01), Wise
Rudberg et al., “High Speed Pipelined Parallel Heffman Decoding”, Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, Jun. 9, 1997 to Jun. 12, 1997, vol. 3, pp. 2080-2083.*
Hauck et al., “Asynchronous VLSI Architectures for Huffman CODECs”, Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, May 31, 1998-Jun. 3, 1998, vol. 5, pp. 542-545.*
Lee et al., A Memory-Based Architecture for Very-High-Throughput Variable Length CODEC design, Proceedings of the 1997 IEEE International Symposium on Circuits and System, Jun. 9, 1997-Jun. 12, 1997, vol. 3, pp. 2096-2099.*
Komori et al., “An Elastic Pipeline Mechanism by Self-Timed Circuits”, IEEE Journal of Solid State Circuits, May 22, 1987-May 23, 1987, vol. 23, iss. 1, pp. 111-117.

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