Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal
Reexamination Certificate
2001-06-01
2003-07-22
Kelley, Chris (Department: 2613)
Pulse or digital communications
Bandwidth reduction or expansion
Television or motion video signal
Reexamination Certificate
active
06597740
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a variable-length encoding and decoding apparatus for encoding or decoding an image compression bit stream according to the MPEG standard.
BACKGROUND OF THE INVENTION
In the image compression bit stream according to the MPEG standard (the details which are described in “Textbook of Recent MPEG” (ASCII) edited by Hiroshi Fujiwara, “All of MPEG-4” (Kogyo chosakai) written and edited by Sukeichi Miki, and the like are avoided), in order to identify a start position of information such as a screen and a type of data included in the bit stream after the start position, a fixed length code having a specific bit pattern (hereinafter, referred to as a start code) is inserted. When compressed image information is decoded, this start code is detected, and decoding processing is performed on the basis of the following information (hereinafter, referred to as “start code value”). In a structure of the start code, as shown in FIG.
7
(
a
), an 8-bit start code value is added to 23 pieces of “0” and a single piece of “1”, 24 bits in total. Taking MPEG4 (Moving Picture Experts Group 4) as an example, the standardized start codes are as shown in FIG.
7
(
b
).
The following measure is taken so as to enable to clearly distinguish the start codes from the other data. Bit patterns which are difficult to appear in the other data are adopted. Further, in the process of encoding the image information, the same bit pattern as that of the start code sometimes results in depending on the combination of the code words. However, in order to avoid an emulation due thereto, in an encoder, a 1-bit bit stream is inserted in the code word which has possibility to be emulated. Further, synchronizing words such as a start code and a sync marker are arranged such that each distance between the heads of synchronizing words becomes a positive integral multiplication of 8 as shown in FIG.
6
.
When a conventional code detecting apparatus detects the synchronizing words as described above, the apparatus detects whether a bit stream having a certain bit length coincides with a pattern of the synchronizing word employing a shift register of 1 bit/cycle or 8 bits/cycle, for example, whether the bit sequence of 32 bits from the head of a shift register coincides with the pattern of the synchronizing word.
There is a case where an overlap is generated between image compression information (fixed length code, variable-length code) in the bit stream and the synchronizing word due to transmission errors and the like coming from the worsening of a communication state.
As an example, a state where the overlap is generated between a variable-length code and the synchronizing word will be described with reference to the drawings. Initially, FIG.
4
(
a
) shows a normal bit stream in which the overlap is not generated. A 32-bit synchronizing word
501
follows a variable-length code
500
. On the other hand, FIG.
4
(
b
) shows a bit stream in which the overlap is generated. The 3-bit data from the least significant bit of a variable-length code
510
and 3 bits from the most significant bit of the following 32-bit synchronizing word
511
overlap with each other. The state as shown in FIG.
4
(
b
) is detected, and further the synchronizing word following the variable-length code is detected, resulting in an efficiency improvement of an image decoding processing and suppressing an image deterioration of a decoded image.
However, in the conventional synchronizing word detecting apparatuses, there are some in which the synchronizing word cannot be detected when the overlap is generated between the bit stream and the synchronizing word in the image compression information (fixed length code, variable-length code). In addition, there are some in which even if the synchronizing word can be detected, the state where the image compression information and the synchronizing word overlap with each other cannot be detected.
The synchronizing word is important information which shows the following image decoding processing. Therefore, non-detection or erroneous detection of the synchronizing word has a strong possibility of affecting the following image decoding processing, and causes an efficiency lowering of the image decoding processing and deteriorating the quality of the decoded image. In addition, such an error that the variable-length code and the synchronizing word overlap with each other cannot be detected. Therefore, there is a case where, when, actually, the image decoding processing should be interrupted immediately after error detection, the processing is kept as it is, thereby generating an erroneous decoded image and deteriorating the quality of an output image.
Furthermore, in the conventional synchronizing word detecting apparatus, searching for the synchronizing word is performed with the data being abandoned, and the above-described processing is kept until the synchronizing word is detected. Therefore, it is impossible for the apparatus to identify whether the synchronizing word exists in the most neighboring byte align point.
SUMMARY OF THE INVENTION
The present invention is made to solve the above-described problems, and it has for its object to provide a variable-length encoding and decoding apparatus which, when the overlap is generated in the image compression information and the synchronizing word, can detect the synchronizing word and can detect an error that the image compression information and the synchronizing word overlap with each other, and further can efficiently identify the presence of the synchronizing word in the most neighboring byte align point.
In order to solve the problems, according to a 1st aspect of the present invention, there is provided a variable-length encoding and decoding apparatus comprising: a register which stores a bit stream of video compression information from an external apparatus; a first shift register which shifts a signal to the high-order direction by n bytes per a machine cycle; first selection means for selecting a vacant section of a successive predetermined bit number in a predetermined section from the least significant bit of the first shift register, and successively storing a signal of the first shift register from the high-order side of the vacant section of the first shift register; a second shift register which shifts the signal to the high-order direction by the optional bit number per a machine cycle; second selection means for selecting a vacant section of the successive predetermined bit number in a predetermined section from the least significant bit of the second shift register, and successively storing a signal of the second shift register from the high-order side of the vacant section of the second shift register; third selection means for selecting a signal of the successive predetermined bit number in the second shift register; variable-length encoding and decoding means for performing decoding and simultaneously outputting code length information which shows a code length of a variable-length code in the case where a signal selected by the third selection means is a variable-length code and can be decoded; fourth selection means for selecting a signal of the successive predetermined bit number from the first shift register to output the same while decoding processing of the variable-length code is performed by the variable-length encoding and decoding means, and outputting a signal input from the third selection means when the decoding processing is completed; synchronizing word detecting means having first code detecting means for comparing the signal of the first shift register selected by the fourth selection means with a specific bit pattern to perform coincidence detection, and second code detecting means for comparing the signal of the second shift register selected by the fourth selection means with the specific bit pattern to perform coincidence detection; specific bit pattern position information management means which, when a signal of the specific bit pattern in the first shift regist
Hashimoto Kohkichi
Imura Koji
Nakamura Tsuyoshi
Bugg George A
Kelley Chris
Matsushita Electric - Industrial Co., Ltd.
Parkhurst & Wendel L.L.P.
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