Variable length decoder system and method

Details Variable length decoder system and method Variable length decoder system and method

2007-09-13

2010-06-01

Jeanglaude, Jean B (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

To or from variable length codes

C341S106000

Reexamination Certificate

active

07728744

ABSTRACT:
Simultaneously decoding one or more variable length code symbols including storing in a bit FIFO at least a portion of a variable length coded bit stream; storing a succession of extracted bit fields of predetermined bit length from the variable length coded bit stream in the bit FIFO; defining at least one inspection field in the extracted bit field, each inspection field identifying at least one variable length code symbol; and storing in look-up table a decode value uniquely addressable by each bit combination of the inspection field for reading out the one or more decode values corresponding to the unique address defined by the inspection field.

REFERENCES:
patent: 3303477 (1967-02-01), Voigt
patent: 3805037 (1974-04-01), Ellison
patent: 3959638 (1976-05-01), Blum et al.
patent: 4757506 (1988-07-01), Heichler
patent: 5031131 (1991-07-01), Mikos
patent: 5062057 (1991-10-01), Blacken et al.
patent: 5101338 (1992-03-01), Fujiwara et al.
patent: 5260898 (1993-11-01), Richardson
patent: 5287511 (1994-02-01), Robinson et al.
patent: 5351047 (1994-09-01), Behlen
patent: 5386523 (1995-01-01), Crook et al.
patent: 5537579 (1996-07-01), Hiroyuki et al.
patent: 5666116 (1997-09-01), Bakhmutsky
patent: 5675332 (1997-10-01), Limberg
patent: 5689452 (1997-11-01), Cameron
patent: 5696941 (1997-12-01), Jung et al.
patent: 5710939 (1998-01-01), Ballachino et al.
patent: 5832290 (1998-11-01), Gostin et al.
patent: 5961640 (1999-10-01), Chambers et al.
patent: 5996057 (1999-11-01), Scales, III et al.
patent: 5996066 (1999-11-01), Yung
patent: 6009499 (1999-12-01), Koppala
patent: 6061749 (2000-05-01), Webb et al.
patent: 6067609 (2000-05-01), Meeker et al.
patent: 6094726 (2000-07-01), Gonion et al.
patent: 6134676 (2000-10-01), VanHuben et al.
patent: 6138208 (2000-10-01), Dhong et al.
patent: 6151705 (2000-11-01), Santhanam
patent: 6223320 (2001-04-01), Dubey et al.
patent: 6230179 (2001-05-01), Dworkin et al.
patent: 6272452 (2001-08-01), Wu et al.
patent: 6285607 (2001-09-01), Sinclair
patent: 6430672 (2002-08-01), Dhong et al.
patent: 6480845 (2002-11-01), Egolf et al.
patent: 6539477 (2003-03-01), Seawright
patent: 6587864 (2003-07-01), Stein et al.
patent: 6757806 (2004-06-01), Shim
patent: 6771196 (2004-08-01), Hsiun
patent: 6829694 (2004-12-01), Stein et al.
patent: 7173985 (2007-02-01), Diaz-Manero et al.
patent: 7187729 (2007-03-01), Nagano
patent: 7424597 (2008-09-01), Lee et al.
patent: 2003/0085822 (2003-05-01), Scheuermann
patent: 2003/0103626 (2003-06-01), Stein et al.
patent: 2003/0133568 (2003-07-01), Stein et al.
patent: 2003/0149857 (2003-08-01), Stein et al.
patent: 2003/0196072 (2003-10-01), Chinnakonda et al.
patent: 2003/0229769 (2003-12-01), Montemayor
patent: 2004/0145942 (2004-07-01), Leijten-Nowak
patent: 2004/0210618 (2004-10-01), Stein et al.
patent: 2005/0086452 (2005-04-01), Ross
patent: 2005/0228966 (2005-10-01), Nakamura
patent: 2005/0267996 (2005-12-01), O'Connor et al.
patent: 2006/0143554 (2006-06-01), Sudhakar et al.
patent: 2006/0271763 (2006-11-01), Pedersen et al.
patent: 2007/0044008 (2007-02-01), Chen et al.
patent: 2007/0089043 (2007-04-01), Chae et al.
patent: 2007/0094474 (2007-04-01), Wilson et al.
patent: 2007/0094483 (2007-04-01), Wilson et al.
patent: 2008/0244237 (2008-10-01), Wilson et al.
Yadav et al., Software-Only Multiple Variable Length Decoding for Real-Time Video on MDSP, 0-7803-8838-0/05 2005 IEEE, pp. 141-142.
“Microsoft Computer Dictionary”, 2002, Microsoft Press, 5th ed., p. 474.
Citron et al. “Accelerating Multi-Media Processing by Implementing Memoing in Multiplication and Division Units,” ACM Sigplan Notices, ACM, Asspociation for Computer Machinery, NY, NY, vol. 33, No. 11, Nov. 1998, pp. 252-261.
Goslin, “A Guide to Using Field Programmable Gate Arrays (FPGAs) for Application-Specific Digital Signal Processing Performance,” [online], Xilinx, Dec. 1995 [retrieved Aug. 19, 2009]. Retrieved from the Internet: <http://www.xilinx.com/appnotes/dspguide.pdf>, 11 pages.
Hendrix et al., “Viterbi Decoding Techniques for the TMS32054x DSP Generation,” Texas Instruments, Application Report SPRA071A-Jan. 2002, pp. 1-8.
Hennessy et al. “Computer Organization and Design: The Hardware/Software Interface” Morgan Kaufmann Publishers, Inc., 2nd ed., 1997, pp. 449-465.
Intel, Pentium Processor Family Developer's Manual, [online], vol. 3, Architecture and Programming Manual, 1995, [retrieved Dec. 7, 2009]. Retrieved from the Internet: <http://download.intel.com/design/pentium/MANUALS/24143004.pdf>, retrieved Dec. 7, 2009, 1032 pages.
Rasheed et al., “Reconfigurable Viterbi Decoder for Mobile Platform,” Mobile Communications Department, Institut Eurecom Sophia Antipolis, France, 3 pages.
Richardson, “Exploiting Trivial and Redundant Computation,” Computer Arithmetic, 1993, Proceedings, 11th Symposium on Windsor, Ont. Canada, Jun. 29-Jul. 2, 1983, Los Alamitos, CA, USA, IEEE Comput. Soc., Jun. 1993, pp. 220-227.
International Search Report for International Application No. PCT/US2006/040510, mailed Oct. 17, 2007, 2 pages.
Written Opinion for International Application No. PCT/US2006/040510, mailed Oct. 17, 2007, 9 pages.
Supplementary European Search Report and Opinion for European Patent Application No. 06817042.2, mailed Nov. 17, 2008, 8 pages.
English translation of Office Action for Chinese Patent Application No. 200680039988.6, mailed Jun. 19, 2009, 7 pages.
International Search Report for International Application No. PCT/US2008/010524, mailed Nov. 28, 2008, 1 page.
Written Opinion for International Application No. PCT/US2008/010524, mailed Nov. 28, 2008, 7 pages.
International Search Report for International Application No. PCT/US2006/040414, mailed Oct. 1, 2007, 1 page.
Written Opinion for International Application No. PCT/US2006/040414, mailed Oct. 1, 2007, 7 pages.
English translation of Office Action for Taiwan Patent Application No. 095139557, mailed Sep. 29, 2009, 5 pages.
Supplementary European Search Report and Opinion for European Patent Application No. 06817002.6, mailed Mar. 17, 2009, 5 pages.
International Search Report for International Application No. PCT/US2008/002914, mailed Jun. 27, 2008, 1 page.
Written Opinion for International Application No. PCT/US2008/002914, mailed Jun. 27, 2008, 4 pages.
International Search Report for International Application No. PCT/US2008/010571, mailed Nov. 25, 2008, 2 pages.
Written Opinion for International Application No. PCT/US2008/010571, mailed Nov. 25, 2008, 4 pages.
English translation of Office Action for Chinese Patent Application No. 200680039988.6, mailed Dec. 4, 2009, 4 pages.

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