Variable length decoder

Details Variable length decoder Variable length decoder

2005-01-11

2005-01-11

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

To or from variable length codes

C341S106000

Reexamination Certificate

active

06842124

ABSTRACT:
Variable length decoding of DCT coefficients in MPEG video data is performed using a standard processor (400) and a small look-up table (LUT530). The processor performs (520) an integer to floating point conversion on a portion the received bitstream (BS). By this step, lengthy codewords with many leading zeros, which are common in the codebook, are represented in a compressed form by the exponent and mantissa fields (EXP, MAN) of the floating point result (FP). The relevant bits are extracted and used as an index (IX) to address the LUT. This avoids cumbersome bit-oriented logic, while also avoiding a very large LUT that would otherwise be required to represent the same codebook. The entire LUT may thus reside in cache memory (410). In a VLIW processor implementation, decoding of one token is pipelined with the inverse scan and inverse quantisation step of the preceding token(s).

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patent: WO 03034746 (2003-04-01), None
“Parallel Variable Length Decoding with Inverse Quantization for Software MPEG-2 Decoders”—D. Ishii et al, IEICE Trans. Fundamentals, vol. E84-A, No. 12, Dec. 2001.
“Design and Hardware Implementation of a Memory Efficient Huffman Decoding”—R. Hashemian. IEEE Transactions on Consumer Electronics, vol. 40, No. 3, Aug. 1994.

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