Variable length coder of a video coder

Coded data generation or conversion – Digital code to digital code converters – To or from variable length codes

Reexamination Certificate

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Details

C341S100000, C341S101000, C348S403100

Reexamination Certificate

active

06339386

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a video coder and more particularly to a variable length coder and encoding method in the video coder. The present invention is especially applicable in wireless communications such as mobile stations or phones which simultaneously request both voice and image transmission services.
DISCUSSION OF RELATED ART
In a communication system, a video coder generally encodes image signals to be transmitted prior to the transmission. The video coder may utilize a variable length coder (VLC) to encode coefficients processed through a discrete cosign transform (DCT) and quantized by a quantizer. A coding system utilizing a VLC is disclosed in “An Entropy Coding System for Digital HDTV Applications,”
IEEE Transactions on Circuits and Systems for Video Technology
, vol. 1, no. 1, pp. 147-55 (March 1991) and is herein incorporated.
Generally, the VLC encodes the input data into variable length codes, concatenates the codes, and segments the codes into a predetermined code length of the VLC. The predetermined code length is greater than or equal to the maximal code length of the VLC.
FIG. 1
shows a typical VLC in the related art including a VLC code generator
10
, a bit packer
20
, and a channel buffer
30
. The VLC code generator
10
generates and transmits the code information and the code length information to the bit packer
20
. The bit packer
20
accumulates the received code information for the duration of the predetermined code length of the VLC and outputs the accumulated code information to the channel buffer
30
. The channel buffer
30
then stores and outputs the bit stream of the code information to a subsequent processor at a constant rate.
Also, a typical construction of the bit packer
20
, shown in
FIG. 2
, includes two barrel shifters
21
and
22
, an accumulator
23
, a plurality of registers
24
-
28
, and a flip-flop (F/F)
29
. To concatenate and segment the code information into the predetermined code length, the bit packer
20
performs bit packing of the code information, the barrel shifter
21
concatenates the to input codes to the bit stream stored in the register and the barrel shifter
22
segments the bit stream according to the predetermined code length. The accumulator
23
adds the input code length and informs the barrel shifter
22
upon attaining the predetermined code length. Namely, an enabling signal is transmitted from the adder
23
to the one bit flip-flop (F/F) each time the accumulator
23
attains the predetermined code length. This signal informs the channel buffer
30
to read and store the codes from the bit packer
20
.
The bit packer
20
as explained above can process one input code per each system clock and is effective for processing high definition broadcasting signals. However, the implementation of the above explained VLC is very complicated. Utilizing two barrel shifters and one adder, the bit packer alone requires numerous logic gates. As a result, the VLC cannot be implemented in a compact device and the power consumption of the VLC is high.
Thus, the VLC in the related art may be effective for devices requiring high speed processing such as digital HDTV, but for compact devices such as mobile phones in mobile communication system which require minimal consumption of power and compact size, the VLC in the related art would not be efficient.
OBJECTIVES OF THE INVENTION
An object of the present invention is to solve at least the problems and disadvantages of the related art.
An object of the present invention is to provide a simplified VLC for a video coder and encoding method. Therefore, an object of the present invention is to provide a simplified bit packer of a VLC.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
To achieve the objects and in accordance with the purposes of the invention, as embodied and broadly described herein, the present VLC includes a VLC code generator generating and outputting code information and code length information based upon the input symbols; a code buffer storing the code information output from the VLC code generator and outputting the code information at a constant rate; a length buffer storing the code length information output from the VLC code generator and outputting the code length information at a constant rate; and a one bit packer transmitting the code information output from the code buffer based upon the code length information output from the length buffer. According to the channel clock, the present bit packer reads the code information and counts the codes for the duration of the code length to output the code information.
In another embodiment, a second bit packer receives the code information from the first bit packer. A channel buffer stores the code information from the second bit packer and outputs the codes at a constant rate.
The encoding method for using the VLC according to the present invention includes storing the input code information and the code length information in a buffer; and outputting the stored code information based upon the code length information.
The bit packer in the related art requires a complicated hardware with numerous logic gates. In contrast, the present invention allows a bit packer with a single parallel-to-serial register and a single counter, thereby requiring low power consumption and allowing a compact size. Thus, the present invention is useful in mobile communication, such as in cellular phones.


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Shaw-Min Lee and Ming-Ting Sun, “An Entropy Coding System for Digital HDT”, IEEE Transactions on Circuits and Systems for Video Technology, vol. 1, No. 1 , Mar. 1991, pp. 147-155.

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