Variable length code processor with encoding and/or decoding

Details Variable length code processor with encoding and/or decoding Variable length code processor with encoding and/or decoding

1999-02-01

2000-11-07

Tokar, Michael

Coded data generation or conversion

Digital code to digital code converters

To or from variable length codes

348426, 3582611, H03M 740

Patent

active

061443220

ABSTRACT:
A variable length code processor is obtained which can perform encoding or decoding process in a plurality of variable length encoding standards. A sequence control section (5) has two control registers (VL.sub.-- MODE and VL.sub.-- CNT). A CPU (2) sets the desired value to the control register (VL.sub.-- MODE) to select a processing content to be performed by a VLC processor (4). A local memory (7) is realized by a 4K-byte RAM to store retrieval tables used in decoding or encoding process. The sequence control section (5) controls a second DCT buffer section (11), an address generating section (12), a DCT generating section (14), VLC generating section (14), a shifter section (15), a VLC buffer section (16), and a VLC pack section (17), so that the process indicated by the control register (VL.sub.-- MODE) is executable.

REFERENCES:
patent: 5400075 (1995-03-01), Savatier
patent: 5481364 (1996-01-01), Ito
patent: 5502493 (1996-03-01), Meyer
patent: 5604498 (1997-02-01), Park
patent: 5604499 (1997-02-01), Miyagoshi et al.
patent: 5623262 (1997-04-01), Normille et al.
patent: 5675331 (1997-10-01), Watanabe et al.
patent: 5764357 (1998-06-01), Dorkser
patent: 5767799 (1998-06-01), Maertens et al.

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