Coded data generation or conversion – Digital code to digital code converters – To or from variable length codes
Patent
1995-01-24
1997-06-24
Williams, Howard L.
Coded data generation or conversion
Digital code to digital code converters
To or from variable length codes
341 65, 365 49, H03M 740
Patent
active
056421141
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention relates to a variable-length code decoding circuit for decoding a compressed image, etc. and to a system for decoding variable-length code using the same.
There is the following literature disclosing a technique for decoding a variable-length code.
Literature: IEEE 1992 Custom Integrated Circuits Conference, "A Video-Rate, JPEG Chip Set" p. 26. 2. 1-26. 2. 4., authored by Daniel A. Luthi, Po Tong, and Peter A. Ruetz.
This literature discloses a technique using a variable-length code as a means for compressing image data or for restoring and decoding the compressed image data.
A variable-length code means a code which is allocated in response to the frequency of occurrence of parameters after the image data has been subjected to an arithmetic operation such as a Discrete Cosine Transform (hereinafter referred to as DCT) operation and a quantization operation. That is, a short code is allocated to a parameter which frequently occurs while occurs a long code is allocated to a parameter which less frequently. By varying the length of the code as mentioned above, the total length for a sequence number of codes can be reduced as a whole, thereby realizing an improvement in the compression rate of the image data.
Since the image display rate on of a TV set or a monitor must be kept at a given value when restoring a dynamic image, the variable length code as set forth above is always required to be restored at a constant rate. It is preferable in practice to decode one variable-length code in one clock cycle. Since image data is required to be processed at high speed in recent years, an improvement in the decoding speed of the variable-length code is important as one means for realizing a high processing speed of the image data.
It is an object of the invention to provide a variable-length code decoding circuit for realizing high operation speed.
It is another object of the invention to provide a variable-length code decoding system for realizing a high operation speed.
SUMMARY OF THE INVENTION
To achieve the above objects, the present invention comprises a data line to which a first data is applied, a storage circuit coupled to the data line for storing a second data wherein the storage circuit collates the first data with the second data and outputting a collating result, a collating result output line to which the collating result is applied, a gate coupled between the storage circuit and the collating result output line for inhibiting the collating result from being output to the collating result output line in response to a control signal, and a control circuit for outputting the control signal.
To achieve the above objects, the present invention comprises a plurality of data lines to which each of a plurality of first code data in a first variable-length code data is applied, a plurality of storage circuits coupled to the plurality of the data lines for storing each of a plurality of second code data of a second variable-length code data wherein the storage circuits collates the first code data with the second code data and outputting a collating result, a collating result output line to which the collating result is applied, a plurality of gates each coupled between the plurality of storage circuits and the collating result output line for inhibiting the collating result from being output to the collating result output line in response to a control signal, and a plurality of control circuits for outputting the control signal.
Further, to achieve the above objects, the present invention comprises a plurality of data lines to which each of a plurality of first code data of a first variable-length code data is applied, a plurality of first storage circuits each coupled to the plurality of the data lines for storing each of a plurality of second code data of a second variable-length code data wherein the plurality of first storage circuits collate the first code data with the second code data and outputting a first collating result, a first collating result
REFERENCES:
patent: 4670858 (1987-06-01), Almy
patent: 5173695 (1992-12-01), Sun et al.
patent: 5245338 (1993-09-01), Sun
patent: 5475389 (1995-12-01), Song et al.
Daniel A. Luthi et al., "A Video-Rate JPEG Chip Set", IEEE 1992 Custom Integrated Circuits Conference, pp. 26.2.1-26.2.4.
Komoto Eiji
Nakamura Takao
OKI Electric Industry Co., Ltd.
Williams Howard L.
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