Variable latency scheme for synchronous memory

Details Variable latency scheme for synchronous memory Variable latency scheme for synchronous memory

1993-12-16

1995-03-28

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Sync/clocking

36518905, 365193, 365194, G11C 700

Patent

active

054023882

ABSTRACT:
The present invention relates to a method of writing or reading a semiconductor random access memory (DRAM or SRAM) having plural sense amplifiers connected to bit lines and having data bus read and write amplifiers, formed of providing a pair of data buses for access by each sense amplifier and each read and write amplifier, reading or writing one data bus while precharging the other data bus during a first read or write cycle, and reading or writing the other data bus while precharging the first data bus in a second read or write cycle following the first read or write cycle.

REFERENCES:
patent: 5206832 (1993-04-01), Yamaguchi et al.
patent: 5208779 (1993-05-01), Walther et al.

Affiliated with

Also associated with

Rating

Variable latency scheme for synchronous memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Variable latency scheme for synchronous memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Variable latency scheme for synchronous memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2256437