Variable latency method and apparatus for floating-point coproce

Details Variable latency method and apparatus for floating-point coproce Variable latency method and apparatus for floating-point coproce

1990-01-19

1991-06-04

Harkcom, Gary V.

Boots, shoes, and leggings

364200, 364736, G06F 738

Patent

active

050219855

ABSTRACT:
A programmable latency (a programmable number of clock cycles) needed for an operation completion. The required latency for a pipe is determined from a formula including the system clock cycle time which the unit will be specified to operate under. The latency is preprogrammed by setting the count of a timer accordingly to provide at least the minimum number of clock cycles necessary to cover the time required to do the computation. Separate timers are independently set for arithmetic logic unit (ALU) operations, multiply operations, logical operations and divide and square root operations.

REFERENCES:
patent: 4612628 (1986-09-01), Beauchamp et al.
patent: 4901267 (1990-02-01), Birman et al.

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